; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -mtriple=amdgcn -mcpu=gfx942 < %s | FileCheck --check-prefix=GFX942 %s

define amdgpu_kernel void @v3i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1) %src2, ptr addrspace(1) nocapture %dst) {
; GFX942-LABEL: v3i8_liveout:
; GFX942:       ; %bb.0: ; %entry
; GFX942-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX942-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX942-NEXT:    v_and_b32_e32 v4, 0x3ff, v0
; GFX942-NEXT:    v_lshlrev_b32_e32 v1, 2, v4
; GFX942-NEXT:    v_mov_b32_e32 v2, 8
; GFX942-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-NEXT:    global_load_dword v3, v1, s[0:1]
; GFX942-NEXT:    s_mov_b32 s4, 0xff0000
; GFX942-NEXT:    v_mov_b32_e32 v0, 0
; GFX942-NEXT:    v_cmp_gt_u32_e32 vcc, 15, v4
; GFX942-NEXT:    s_waitcnt vmcnt(0)
; GFX942-NEXT:    v_lshrrev_b32_sdwa v5, v2, v3 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX942-NEXT:    s_nop 0
; GFX942-NEXT:    v_or_b32_sdwa v5, v3, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX942-NEXT:    v_and_b32_e32 v5, 0xffff, v5
; GFX942-NEXT:    v_and_or_b32 v3, v3, s4, v5
; GFX942-NEXT:    s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT:    s_cbranch_execz .LBB0_2
; GFX942-NEXT:  ; %bb.1: ; %bb.1
; GFX942-NEXT:    global_load_dword v1, v1, s[2:3]
; GFX942-NEXT:    s_waitcnt vmcnt(0)
; GFX942-NEXT:    v_lshrrev_b32_sdwa v2, v2, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX942-NEXT:    s_nop 0
; GFX942-NEXT:    v_or_b32_sdwa v2, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX942-NEXT:    v_and_b32_e32 v2, 0xffff, v2
; GFX942-NEXT:    v_and_or_b32 v3, v1, s4, v2
; GFX942-NEXT:  .LBB0_2: ; %bb.2
; GFX942-NEXT:    s_or_b64 exec, exec, s[0:1]
; GFX942-NEXT:    global_store_byte_d16_hi v0, v3, s[6:7] offset:2
; GFX942-NEXT:    global_store_short v0, v3, s[6:7]
; GFX942-NEXT:    s_endpgm
entry:
  %idx = call i32 @llvm.amdgcn.workitem.id.x()
  %gep1 = getelementptr <3 x i8>, ptr addrspace(1) %src1, i32 %idx
  %vec1 = load <3 x i8>, ptr addrspace(1) %gep1
  %gep2 = getelementptr <3 x i8>, ptr addrspace(1) %src2, i32 %idx
  %vec2 = load <3 x i8>, ptr addrspace(1) %gep2
  %cmp = icmp ult i32 %idx, 15
  br i1 %cmp, label %bb.1, label %bb.2
bb.1:
  br label %bb.2

bb.2:
  %tmp5 = phi <3 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ]
  store <3 x i8> %tmp5, ptr addrspace(1) %dst, align 4
  ret void
}

define amdgpu_kernel void @v4i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1) %src2, ptr addrspace(1) nocapture %dst) {
; GFX942-LABEL: v4i8_liveout:
; GFX942:       ; %bb.0: ; %entry
; GFX942-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX942-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX942-NEXT:    v_and_b32_e32 v3, 0x3ff, v0
; GFX942-NEXT:    v_lshlrev_b32_e32 v1, 2, v3
; GFX942-NEXT:    v_mov_b32_e32 v0, 0
; GFX942-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-NEXT:    global_load_dword v2, v1, s[0:1]
; GFX942-NEXT:    v_cmp_gt_u32_e32 vcc, 15, v3
; GFX942-NEXT:    s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT:    s_cbranch_execz .LBB1_2
; GFX942-NEXT:  ; %bb.1: ; %bb.1
; GFX942-NEXT:    global_load_dword v2, v1, s[2:3]
; GFX942-NEXT:  .LBB1_2: ; %bb.2
; GFX942-NEXT:    s_or_b64 exec, exec, s[0:1]
; GFX942-NEXT:    s_waitcnt vmcnt(0)
; GFX942-NEXT:    global_store_dword v0, v2, s[6:7]
; GFX942-NEXT:    s_endpgm
entry:
  %idx = call i32 @llvm.amdgcn.workitem.id.x()
  %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
  %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
  %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
  %vec2 = load <4 x i8>, ptr addrspace(1) %gep2
  %cmp = icmp ult i32 %idx, 15
  br i1 %cmp, label %bb.1, label %bb.2
bb.1:
  br label %bb.2

bb.2:
  %tmp5 = phi <4 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ]
  store <4 x i8> %tmp5, ptr addrspace(1) %dst, align 4
  ret void
}

define amdgpu_kernel void @v5i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1) %src2, ptr addrspace(1) nocapture %dst) {
; GFX942-LABEL: v5i8_liveout:
; GFX942:       ; %bb.0: ; %entry
; GFX942-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX942-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX942-NEXT:    v_and_b32_e32 v4, 0x3ff, v0
; GFX942-NEXT:    v_lshlrev_b32_e32 v3, 3, v4
; GFX942-NEXT:    v_mov_b32_e32 v2, 0
; GFX942-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-NEXT:    global_load_dwordx2 v[0:1], v3, s[0:1]
; GFX942-NEXT:    v_cmp_gt_u32_e32 vcc, 15, v4
; GFX942-NEXT:    s_waitcnt vmcnt(0)
; GFX942-NEXT:    v_and_b32_e32 v1, 0xff, v1
; GFX942-NEXT:    s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT:    s_cbranch_execz .LBB2_2
; GFX942-NEXT:  ; %bb.1: ; %bb.1
; GFX942-NEXT:    global_load_dwordx2 v[0:1], v3, s[2:3]
; GFX942-NEXT:    s_waitcnt vmcnt(0)
; GFX942-NEXT:    v_and_b32_e32 v1, 0xff, v1
; GFX942-NEXT:  .LBB2_2: ; %bb.2
; GFX942-NEXT:    s_or_b64 exec, exec, s[0:1]
; GFX942-NEXT:    global_store_byte v2, v1, s[6:7] offset:4
; GFX942-NEXT:    global_store_dword v2, v0, s[6:7]
; GFX942-NEXT:    s_endpgm
entry:
  %idx = call i32 @llvm.amdgcn.workitem.id.x()
  %gep1 = getelementptr <5 x i8>, ptr addrspace(1) %src1, i32 %idx
  %vec1 = load <5 x i8>, ptr addrspace(1) %gep1
  %gep2 = getelementptr <5 x i8>, ptr addrspace(1) %src2, i32 %idx
  %vec2 = load <5 x i8>, ptr addrspace(1) %gep2
  %cmp = icmp ult i32 %idx, 15
  br i1 %cmp, label %bb.1, label %bb.2
bb.1:
  br label %bb.2

bb.2:
  %tmp5 = phi <5 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ]
  store <5 x i8> %tmp5, ptr addrspace(1) %dst, align 4
  ret void
}

define amdgpu_kernel void @v8i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1) %src2, ptr addrspace(1) nocapture %dst) {
; GFX942-LABEL: v8i8_liveout:
; GFX942:       ; %bb.0: ; %entry
; GFX942-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX942-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX942-NEXT:    v_and_b32_e32 v4, 0x3ff, v0
; GFX942-NEXT:    v_lshlrev_b32_e32 v1, 3, v4
; GFX942-NEXT:    v_mov_b32_e32 v0, 0
; GFX942-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-NEXT:    global_load_dwordx2 v[2:3], v1, s[0:1]
; GFX942-NEXT:    v_cmp_gt_u32_e32 vcc, 15, v4
; GFX942-NEXT:    s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT:    s_cbranch_execz .LBB3_2
; GFX942-NEXT:  ; %bb.1: ; %bb.1
; GFX942-NEXT:    global_load_dwordx2 v[2:3], v1, s[2:3]
; GFX942-NEXT:  .LBB3_2: ; %bb.2
; GFX942-NEXT:    s_or_b64 exec, exec, s[0:1]
; GFX942-NEXT:    s_waitcnt vmcnt(0)
; GFX942-NEXT:    global_store_dwordx2 v0, v[2:3], s[6:7]
; GFX942-NEXT:    s_endpgm
entry:
  %idx = call i32 @llvm.amdgcn.workitem.id.x()
  %gep1 = getelementptr <8 x i8>, ptr addrspace(1) %src1, i32 %idx
  %vec1 = load <8 x i8>, ptr addrspace(1) %gep1
  %gep2 = getelementptr <8 x i8>, ptr addrspace(1) %src2, i32 %idx
  %vec2 = load <8 x i8>, ptr addrspace(1) %gep2
  %cmp = icmp ult i32 %idx, 15
  br i1 %cmp, label %bb.1, label %bb.2
bb.1:
  br label %bb.2

bb.2:
  %tmp5 = phi <8 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ]
  store <8 x i8> %tmp5, ptr addrspace(1) %dst, align 4
  ret void
}

define amdgpu_kernel void @v16i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1) %src2, ptr addrspace(1) nocapture %dst) {
; GFX942-LABEL: v16i8_liveout:
; GFX942:       ; %bb.0: ; %entry
; GFX942-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX942-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX942-NEXT:    v_and_b32_e32 v6, 0x3ff, v0
; GFX942-NEXT:    v_lshlrev_b32_e32 v1, 4, v6
; GFX942-NEXT:    v_mov_b32_e32 v0, 0
; GFX942-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-NEXT:    global_load_dwordx4 v[2:5], v1, s[0:1]
; GFX942-NEXT:    v_cmp_gt_u32_e32 vcc, 15, v6
; GFX942-NEXT:    s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT:    s_cbranch_execz .LBB4_2
; GFX942-NEXT:  ; %bb.1: ; %bb.1
; GFX942-NEXT:    global_load_dwordx4 v[2:5], v1, s[2:3]
; GFX942-NEXT:  .LBB4_2: ; %bb.2
; GFX942-NEXT:    s_or_b64 exec, exec, s[0:1]
; GFX942-NEXT:    s_waitcnt vmcnt(0)
; GFX942-NEXT:    global_store_dwordx4 v0, v[2:5], s[6:7]
; GFX942-NEXT:    s_endpgm
entry:
  %idx = call i32 @llvm.amdgcn.workitem.id.x()
  %gep1 = getelementptr <16 x i8>, ptr addrspace(1) %src1, i32 %idx
  %vec1 = load <16 x i8>, ptr addrspace(1) %gep1
  %gep2 = getelementptr <16 x i8>, ptr addrspace(1) %src2, i32 %idx
  %vec2 = load <16 x i8>, ptr addrspace(1) %gep2
  %cmp = icmp ult i32 %idx, 15
  br i1 %cmp, label %bb.1, label %bb.2
bb.1:
  br label %bb.2

bb.2:
  %tmp5 = phi <16 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ]
  store <16 x i8> %tmp5, ptr addrspace(1) %dst, align 4
  ret void
}

define amdgpu_kernel void @v32i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1) %src2, ptr addrspace(1) nocapture %dst) {
; GFX942-LABEL: v32i8_liveout:
; GFX942:       ; %bb.0: ; %entry
; GFX942-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX942-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX942-NEXT:    v_and_b32_e32 v10, 0x3ff, v0
; GFX942-NEXT:    v_lshlrev_b32_e32 v1, 5, v10
; GFX942-NEXT:    v_mov_b32_e32 v0, 0
; GFX942-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-NEXT:    global_load_dwordx4 v[6:9], v1, s[0:1] offset:16
; GFX942-NEXT:    global_load_dwordx4 v[2:5], v1, s[0:1]
; GFX942-NEXT:    v_cmp_gt_u32_e32 vcc, 15, v10
; GFX942-NEXT:    s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT:    s_cbranch_execz .LBB5_2
; GFX942-NEXT:  ; %bb.1: ; %bb.1
; GFX942-NEXT:    global_load_dwordx4 v[6:9], v1, s[2:3] offset:16
; GFX942-NEXT:    global_load_dwordx4 v[2:5], v1, s[2:3]
; GFX942-NEXT:  .LBB5_2: ; %bb.2
; GFX942-NEXT:    s_or_b64 exec, exec, s[0:1]
; GFX942-NEXT:    s_waitcnt vmcnt(1)
; GFX942-NEXT:    global_store_dwordx4 v0, v[6:9], s[6:7] offset:16
; GFX942-NEXT:    s_waitcnt vmcnt(1)
; GFX942-NEXT:    global_store_dwordx4 v0, v[2:5], s[6:7]
; GFX942-NEXT:    s_endpgm
entry:
  %idx = call i32 @llvm.amdgcn.workitem.id.x()
  %gep1 = getelementptr <32 x i8>, ptr addrspace(1) %src1, i32 %idx
  %vec1 = load <32 x i8>, ptr addrspace(1) %gep1
  %gep2 = getelementptr <32 x i8>, ptr addrspace(1) %src2, i32 %idx
  %vec2 = load <32 x i8>, ptr addrspace(1) %gep2
  %cmp = icmp ult i32 %idx, 15
  br i1 %cmp, label %bb.1, label %bb.2
bb.1:
  br label %bb.2

bb.2:
  %tmp5 = phi <32 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ]
  store <32 x i8> %tmp5, ptr addrspace(1) %dst, align 4
  ret void
}

define amdgpu_kernel void @v256i8_liveout(ptr addrspace(1) %src1, ptr addrspace(1) %src2, ptr addrspace(1) nocapture %dst) {
; GFX942-LABEL: v256i8_liveout:
; GFX942:       ; %bb.0: ; %entry
; GFX942-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX942-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX942-NEXT:    v_and_b32_e32 v62, 0x3ff, v0
; GFX942-NEXT:    v_lshlrev_b32_e32 v1, 3, v62
; GFX942-NEXT:    v_mov_b32_e32 v0, 0
; GFX942-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-NEXT:    global_load_dwordx4 v[30:33], v1, s[0:1] offset:240
; GFX942-NEXT:    global_load_dwordx4 v[26:29], v1, s[0:1] offset:224
; GFX942-NEXT:    global_load_dwordx4 v[22:25], v1, s[0:1] offset:208
; GFX942-NEXT:    global_load_dwordx4 v[18:21], v1, s[0:1] offset:192
; GFX942-NEXT:    global_load_dwordx4 v[14:17], v1, s[0:1] offset:176
; GFX942-NEXT:    global_load_dwordx4 v[10:13], v1, s[0:1] offset:160
; GFX942-NEXT:    global_load_dwordx4 v[6:9], v1, s[0:1] offset:144
; GFX942-NEXT:    global_load_dwordx4 v[2:5], v1, s[0:1] offset:128
; GFX942-NEXT:    global_load_dwordx4 a[0:3], v1, s[0:1] offset:112
; GFX942-NEXT:    global_load_dwordx4 v[58:61], v1, s[0:1] offset:96
; GFX942-NEXT:    global_load_dwordx4 v[54:57], v1, s[0:1] offset:80
; GFX942-NEXT:    global_load_dwordx4 v[50:53], v1, s[0:1] offset:64
; GFX942-NEXT:    global_load_dwordx4 v[46:49], v1, s[0:1] offset:48
; GFX942-NEXT:    global_load_dwordx4 v[42:45], v1, s[0:1] offset:32
; GFX942-NEXT:    global_load_dwordx4 v[38:41], v1, s[0:1] offset:16
; GFX942-NEXT:    global_load_dwordx4 v[34:37], v1, s[0:1]
; GFX942-NEXT:    v_cmp_gt_u32_e32 vcc, 15, v62
; GFX942-NEXT:    s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT:    s_cbranch_execz .LBB6_2
; GFX942-NEXT:  ; %bb.1: ; %bb.1
; GFX942-NEXT:    global_load_dwordx4 v[30:33], v1, s[2:3] offset:240
; GFX942-NEXT:    global_load_dwordx4 v[26:29], v1, s[2:3] offset:224
; GFX942-NEXT:    global_load_dwordx4 v[22:25], v1, s[2:3] offset:208
; GFX942-NEXT:    global_load_dwordx4 v[18:21], v1, s[2:3] offset:192
; GFX942-NEXT:    global_load_dwordx4 v[14:17], v1, s[2:3] offset:176
; GFX942-NEXT:    global_load_dwordx4 v[10:13], v1, s[2:3] offset:160
; GFX942-NEXT:    global_load_dwordx4 v[6:9], v1, s[2:3] offset:144
; GFX942-NEXT:    global_load_dwordx4 v[2:5], v1, s[2:3] offset:128
; GFX942-NEXT:    global_load_dwordx4 a[0:3], v1, s[2:3] offset:112
; GFX942-NEXT:    global_load_dwordx4 v[58:61], v1, s[2:3] offset:96
; GFX942-NEXT:    global_load_dwordx4 v[54:57], v1, s[2:3] offset:80
; GFX942-NEXT:    global_load_dwordx4 v[50:53], v1, s[2:3] offset:64
; GFX942-NEXT:    global_load_dwordx4 v[46:49], v1, s[2:3] offset:48
; GFX942-NEXT:    global_load_dwordx4 v[42:45], v1, s[2:3] offset:32
; GFX942-NEXT:    global_load_dwordx4 v[38:41], v1, s[2:3] offset:16
; GFX942-NEXT:    global_load_dwordx4 v[34:37], v1, s[2:3]
; GFX942-NEXT:  .LBB6_2: ; %bb.2
; GFX942-NEXT:    s_or_b64 exec, exec, s[0:1]
; GFX942-NEXT:    s_waitcnt vmcnt(7)
; GFX942-NEXT:    global_store_dwordx4 v0, a[0:3], s[6:7] offset:112
; GFX942-NEXT:    s_waitcnt vmcnt(7)
; GFX942-NEXT:    global_store_dwordx4 v0, v[58:61], s[6:7] offset:96
; GFX942-NEXT:    s_waitcnt vmcnt(7)
; GFX942-NEXT:    global_store_dwordx4 v0, v[54:57], s[6:7] offset:80
; GFX942-NEXT:    s_waitcnt vmcnt(7)
; GFX942-NEXT:    global_store_dwordx4 v0, v[50:53], s[6:7] offset:64
; GFX942-NEXT:    s_waitcnt vmcnt(7)
; GFX942-NEXT:    global_store_dwordx4 v0, v[46:49], s[6:7] offset:48
; GFX942-NEXT:    s_waitcnt vmcnt(7)
; GFX942-NEXT:    global_store_dwordx4 v0, v[42:45], s[6:7] offset:32
; GFX942-NEXT:    s_waitcnt vmcnt(7)
; GFX942-NEXT:    global_store_dwordx4 v0, v[38:41], s[6:7] offset:16
; GFX942-NEXT:    s_waitcnt vmcnt(7)
; GFX942-NEXT:    global_store_dwordx4 v0, v[34:37], s[6:7]
; GFX942-NEXT:    global_store_dwordx4 v0, v[30:33], s[6:7] offset:240
; GFX942-NEXT:    global_store_dwordx4 v0, v[26:29], s[6:7] offset:224
; GFX942-NEXT:    global_store_dwordx4 v0, v[22:25], s[6:7] offset:208
; GFX942-NEXT:    global_store_dwordx4 v0, v[18:21], s[6:7] offset:192
; GFX942-NEXT:    global_store_dwordx4 v0, v[14:17], s[6:7] offset:176
; GFX942-NEXT:    global_store_dwordx4 v0, v[10:13], s[6:7] offset:160
; GFX942-NEXT:    global_store_dwordx4 v0, v[6:9], s[6:7] offset:144
; GFX942-NEXT:    global_store_dwordx4 v0, v[2:5], s[6:7] offset:128
; GFX942-NEXT:    s_endpgm
entry:
  %idx = call i32 @llvm.amdgcn.workitem.id.x()
  %gep1 = getelementptr <8 x i8>, ptr addrspace(1) %src1, i32 %idx
  %vec1 = load <256 x i8>, ptr addrspace(1) %gep1
  %gep2 = getelementptr <8 x i8>, ptr addrspace(1) %src2, i32 %idx
  %vec2 = load <256 x i8>, ptr addrspace(1) %gep2
  %cmp = icmp ult i32 %idx, 15
  br i1 %cmp, label %bb.1, label %bb.2
bb.1:
  br label %bb.2

bb.2:
  %tmp5 = phi <256 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ]
  store <256 x i8> %tmp5, ptr addrspace(1) %dst, align 4
  ret void
}

define amdgpu_kernel void @repeat_successor(i32 %in, ptr addrspace(1) %src1, ptr addrspace(1) %src2, ptr addrspace(1) nocapture %dst) {
; GFX942-LABEL: repeat_successor:
; GFX942:       ; %bb.0: ; %entry
; GFX942-NEXT:    s_load_dword s8, s[4:5], 0x24
; GFX942-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x2c
; GFX942-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x3c
; GFX942-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
; GFX942-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-NEXT:    s_cmp_lt_i32 s8, 3
; GFX942-NEXT:    s_cbranch_scc0 .LBB7_3
; GFX942-NEXT:  ; %bb.1: ; %LeafBlock
; GFX942-NEXT:    s_cmp_gt_i32 s8, 0
; GFX942-NEXT:    s_cbranch_scc0 .LBB7_6
; GFX942-NEXT:  ; %bb.2:
; GFX942-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX942-NEXT:    global_load_dword v0, v0, s[0:1]
; GFX942-NEXT:    s_branch .LBB7_5
; GFX942-NEXT:  .LBB7_3: ; %LeafBlock5
; GFX942-NEXT:    s_cmp_eq_u32 s8, 3
; GFX942-NEXT:    s_cbranch_scc0 .LBB7_6
; GFX942-NEXT:  ; %bb.4: ; %sw.bb5
; GFX942-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
; GFX942-NEXT:    global_load_dword v0, v0, s[2:3]
; GFX942-NEXT:  .LBB7_5: ; %return.sink.split
; GFX942-NEXT:    v_mov_b32_e32 v1, 0
; GFX942-NEXT:    s_waitcnt vmcnt(0)
; GFX942-NEXT:    global_store_dword v1, v0, s[6:7]
; GFX942-NEXT:  .LBB7_6: ; %return
; GFX942-NEXT:    s_endpgm
entry:
  %idx = call i32 @llvm.amdgcn.workitem.id.x()
  %gep1 = getelementptr <4 x i8>, ptr addrspace(1) %src1, i32 %idx
  %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
  %gep2 = getelementptr <4 x i8>, ptr addrspace(1) %src2, i32 %idx
  %vec2 = load <4 x i8>, ptr addrspace(1) %gep2
  switch i32 %in, label %return [
  i32 1, label %return.sink.split
  i32 2, label %return.sink.split
  i32 3, label %sw.bb5
  ]

sw.bb5:
  br label %return.sink.split

return.sink.split:
  %tmp5 = phi <4 x i8> [ %vec2, %sw.bb5 ], [ %vec1, %entry ], [ %vec1, %entry ]
  store <4 x i8> %tmp5, ptr addrspace(1) %dst, align 4
  ret void

return:
  ret void
}

define amdgpu_kernel void @v8i8_phi_chain(ptr addrspace(1) %src1, ptr addrspace(1) %src2, ptr addrspace(1) nocapture %dst0, ptr addrspace(1) nocapture %dst1) {
; GFX942-LABEL: v8i8_phi_chain:
; GFX942:       ; %bb.0: ; %entry
; GFX942-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x24
; GFX942-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
; GFX942-NEXT:    v_lshlrev_b32_e32 v1, 3, v0
; GFX942-NEXT:    v_cmp_lt_u32_e64 s[0:1], 14, v0
; GFX942-NEXT:    v_cmp_gt_u32_e32 vcc, 15, v0
; GFX942-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-NEXT:    global_load_dwordx2 v[2:3], v1, s[8:9]
; GFX942-NEXT:    s_and_saveexec_b64 s[2:3], vcc
; GFX942-NEXT:    s_cbranch_execz .LBB8_2
; GFX942-NEXT:  ; %bb.1: ; %bb.1
; GFX942-NEXT:    global_load_dwordx2 v[2:3], v1, s[10:11]
; GFX942-NEXT:    v_cmp_gt_u32_e32 vcc, 7, v0
; GFX942-NEXT:    s_andn2_b64 s[0:1], s[0:1], exec
; GFX942-NEXT:    s_and_b64 s[4:5], vcc, exec
; GFX942-NEXT:    s_or_b64 s[0:1], s[0:1], s[4:5]
; GFX942-NEXT:  .LBB8_2: ; %Flow
; GFX942-NEXT:    s_or_b64 exec, exec, s[2:3]
; GFX942-NEXT:    s_and_saveexec_b64 s[2:3], s[0:1]
; GFX942-NEXT:    s_cbranch_execz .LBB8_4
; GFX942-NEXT:  ; %bb.3: ; %bb.2
; GFX942-NEXT:    v_mov_b32_e32 v0, 0
; GFX942-NEXT:    s_waitcnt vmcnt(0)
; GFX942-NEXT:    global_store_dwordx2 v0, v[2:3], s[12:13]
; GFX942-NEXT:  .LBB8_4: ; %bb.3
; GFX942-NEXT:    s_or_b64 exec, exec, s[2:3]
; GFX942-NEXT:    v_mov_b32_e32 v0, 0
; GFX942-NEXT:    s_waitcnt vmcnt(0)
; GFX942-NEXT:    global_store_dwordx2 v0, v[2:3], s[14:15]
; GFX942-NEXT:    s_endpgm
entry:
  %idx = call i32 @llvm.amdgcn.workitem.id.x()
  %gep1 = getelementptr <8 x i8>, ptr addrspace(1) %src1, i32 %idx
  %vec1 = load <8 x i8>, ptr addrspace(1) %gep1
  %gep2 = getelementptr <8 x i8>, ptr addrspace(1) %src2, i32 %idx
  %vec2 = load <8 x i8>, ptr addrspace(1) %gep2
  %cmp = icmp ult i32 %idx, 15
  br i1 %cmp, label %bb.1, label %bb.2
bb.1:
  %cmp2 = icmp ult i32 %idx, 7
  br i1 %cmp2, label %bb.2, label %bb.3

bb.2:
  %tmp5 = phi <8 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ]
  store <8 x i8> %tmp5, ptr addrspace(1) %dst0, align 4
  br label %bb.3

bb.3:
  %tmp7 = phi <8 x i8> [ %vec2, %bb.1], [%tmp5, %bb.2]
  store <8 x i8> %tmp7, ptr addrspace(1) %dst1, align 4
  ret void
}


define amdgpu_kernel void @v8i8_phi_zeroinit(ptr addrspace(1) %src1, ptr addrspace(1) %src2, ptr addrspace(1) nocapture %dst0, ptr addrspace(1) nocapture %dst1) {
; GFX942-LABEL: v8i8_phi_zeroinit:
; GFX942:       ; %bb.0: ; %entry
; GFX942-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x24
; GFX942-NEXT:    v_and_b32_e32 v0, 0x3ff, v0
; GFX942-NEXT:    v_lshlrev_b32_e32 v1, 3, v0
; GFX942-NEXT:    v_cmp_lt_u32_e64 s[0:1], 14, v0
; GFX942-NEXT:    v_cmp_gt_u32_e32 vcc, 15, v0
; GFX942-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-NEXT:    global_load_dwordx2 v[2:3], v1, s[8:9]
; GFX942-NEXT:    ; implicit-def: $vgpr4_vgpr5
; GFX942-NEXT:    s_and_saveexec_b64 s[2:3], vcc
; GFX942-NEXT:    s_cbranch_execz .LBB9_2
; GFX942-NEXT:  ; %bb.1: ; %bb.1
; GFX942-NEXT:    global_load_dwordx2 v[4:5], v1, s[10:11]
; GFX942-NEXT:    v_cmp_gt_u32_e32 vcc, 7, v0
; GFX942-NEXT:    s_waitcnt vmcnt(1)
; GFX942-NEXT:    v_mov_b32_e32 v2, 0
; GFX942-NEXT:    s_andn2_b64 s[0:1], s[0:1], exec
; GFX942-NEXT:    s_and_b64 s[4:5], vcc, exec
; GFX942-NEXT:    v_mov_b32_e32 v3, v2
; GFX942-NEXT:    s_or_b64 s[0:1], s[0:1], s[4:5]
; GFX942-NEXT:  .LBB9_2: ; %Flow
; GFX942-NEXT:    s_or_b64 exec, exec, s[2:3]
; GFX942-NEXT:    s_and_saveexec_b64 s[2:3], s[0:1]
; GFX942-NEXT:    s_cbranch_execz .LBB9_4
; GFX942-NEXT:  ; %bb.3: ; %bb.2
; GFX942-NEXT:    v_mov_b32_e32 v0, 0
; GFX942-NEXT:    s_waitcnt vmcnt(0)
; GFX942-NEXT:    v_mov_b64_e32 v[4:5], v[2:3]
; GFX942-NEXT:    global_store_dwordx2 v0, v[2:3], s[12:13]
; GFX942-NEXT:  .LBB9_4: ; %bb.3
; GFX942-NEXT:    s_or_b64 exec, exec, s[2:3]
; GFX942-NEXT:    v_mov_b32_e32 v0, 0
; GFX942-NEXT:    s_waitcnt vmcnt(0)
; GFX942-NEXT:    global_store_dwordx2 v0, v[4:5], s[14:15]
; GFX942-NEXT:    s_endpgm
entry:
  %idx = call i32 @llvm.amdgcn.workitem.id.x()
  %gep1 = getelementptr <8 x i8>, ptr addrspace(1) %src1, i32 %idx
  %vec1 = load <8 x i8>, ptr addrspace(1) %gep1
  %gep2 = getelementptr <8 x i8>, ptr addrspace(1) %src2, i32 %idx
  %vec2 = load <8 x i8>, ptr addrspace(1) %gep2
  %cmp = icmp ult i32 %idx, 15
  br i1 %cmp, label %bb.1, label %bb.2
bb.1:
  %cmp2 = icmp ult i32 %idx, 7
  br i1 %cmp2, label %bb.2, label %bb.3

bb.2:
  %tmp5 = phi <8 x i8> [ %vec1, %entry ], [ zeroinitializer, %bb.1 ]
  store <8 x i8> %tmp5, ptr addrspace(1) %dst0, align 4
  br label %bb.3

bb.3:
  %tmp7 = phi <8 x i8> [ %vec2, %bb.1], [%tmp5, %bb.2]
  store <8 x i8> %tmp7, ptr addrspace(1) %dst1, align 4
  ret void
}

define amdgpu_kernel void @v8i8_phi_const(ptr addrspace(1) %src1, ptr addrspace(1) %src2, ptr addrspace(1) nocapture %dst0, ptr addrspace(1) nocapture %dst1) {
; GFX942-LABEL: v8i8_phi_const:
; GFX942:       ; %bb.0: ; %entry
; GFX942-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x24
; GFX942-NEXT:    v_and_b32_e32 v16, 0x3ff, v0
; GFX942-NEXT:    v_lshlrev_b32_e32 v3, 3, v16
; GFX942-NEXT:    v_cmp_lt_u32_e64 s[0:1], 14, v16
; GFX942-NEXT:    v_cmp_gt_u32_e32 vcc, 15, v16
; GFX942-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-NEXT:    global_load_dwordx2 v[0:1], v3, s[8:9]
; GFX942-NEXT:    ; implicit-def: $vgpr2
; GFX942-NEXT:    ; implicit-def: $vgpr12
; GFX942-NEXT:    ; implicit-def: $vgpr10
; GFX942-NEXT:    ; implicit-def: $vgpr13
; GFX942-NEXT:    ; implicit-def: $vgpr14
; GFX942-NEXT:    ; implicit-def: $vgpr11
; GFX942-NEXT:    ; implicit-def: $vgpr15
; GFX942-NEXT:    s_waitcnt vmcnt(0)
; GFX942-NEXT:    v_lshrrev_b32_e32 v4, 24, v1
; GFX942-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
; GFX942-NEXT:    v_lshrrev_b32_e32 v6, 8, v1
; GFX942-NEXT:    v_lshrrev_b32_e32 v7, 24, v0
; GFX942-NEXT:    v_lshrrev_b32_e32 v8, 16, v0
; GFX942-NEXT:    v_lshrrev_b32_e32 v9, 8, v0
; GFX942-NEXT:    s_and_saveexec_b64 s[2:3], vcc
; GFX942-NEXT:    s_cbranch_execz .LBB10_2
; GFX942-NEXT:  ; %bb.1: ; %bb.1
; GFX942-NEXT:    global_load_dwordx2 v[2:3], v3, s[10:11]
; GFX942-NEXT:    v_cmp_gt_u32_e32 vcc, 7, v16
; GFX942-NEXT:    s_andn2_b64 s[0:1], s[0:1], exec
; GFX942-NEXT:    s_and_b64 s[4:5], vcc, exec
; GFX942-NEXT:    v_mov_b32_e32 v4, 8
; GFX942-NEXT:    v_mov_b32_e32 v5, 7
; GFX942-NEXT:    v_mov_b32_e32 v6, 6
; GFX942-NEXT:    v_mov_b32_e32 v1, 5
; GFX942-NEXT:    v_mov_b32_e32 v7, 4
; GFX942-NEXT:    v_mov_b32_e32 v8, 3
; GFX942-NEXT:    v_mov_b32_e32 v9, 2
; GFX942-NEXT:    v_mov_b32_e32 v0, 1
; GFX942-NEXT:    s_or_b64 s[0:1], s[0:1], s[4:5]
; GFX942-NEXT:    s_waitcnt vmcnt(0)
; GFX942-NEXT:    v_lshrrev_b32_e32 v15, 24, v3
; GFX942-NEXT:    v_lshrrev_b32_e32 v11, 16, v3
; GFX942-NEXT:    v_lshrrev_b32_e32 v14, 8, v3
; GFX942-NEXT:    v_lshrrev_b32_e32 v13, 24, v2
; GFX942-NEXT:    v_lshrrev_b32_e32 v10, 16, v2
; GFX942-NEXT:    v_lshrrev_b32_e32 v12, 8, v2
; GFX942-NEXT:  .LBB10_2: ; %Flow
; GFX942-NEXT:    s_or_b64 exec, exec, s[2:3]
; GFX942-NEXT:    s_and_saveexec_b64 s[2:3], s[0:1]
; GFX942-NEXT:    s_cbranch_execz .LBB10_4
; GFX942-NEXT:  ; %bb.3: ; %bb.2
; GFX942-NEXT:    v_lshlrev_b16_e32 v2, 8, v9
; GFX942-NEXT:    v_lshlrev_b16_e32 v3, 8, v7
; GFX942-NEXT:    v_or_b32_sdwa v2, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX942-NEXT:    v_or_b32_sdwa v3, v8, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX942-NEXT:    v_lshlrev_b16_e32 v11, 8, v4
; GFX942-NEXT:    v_or_b32_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX942-NEXT:    v_lshlrev_b16_e32 v3, 8, v6
; GFX942-NEXT:    v_or_b32_sdwa v3, v1, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX942-NEXT:    v_or_b32_sdwa v11, v5, v11 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX942-NEXT:    v_mov_b32_e32 v10, 0
; GFX942-NEXT:    v_or_b32_sdwa v3, v3, v11 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX942-NEXT:    global_store_dwordx2 v10, v[2:3], s[12:13]
; GFX942-NEXT:    v_mov_b32_e32 v2, v0
; GFX942-NEXT:    v_mov_b32_e32 v12, v9
; GFX942-NEXT:    v_mov_b32_e32 v10, v8
; GFX942-NEXT:    v_mov_b32_e32 v13, v7
; GFX942-NEXT:    v_mov_b32_e32 v3, v1
; GFX942-NEXT:    v_mov_b32_e32 v14, v6
; GFX942-NEXT:    v_mov_b32_e32 v11, v5
; GFX942-NEXT:    v_mov_b32_e32 v15, v4
; GFX942-NEXT:  .LBB10_4: ; %bb.3
; GFX942-NEXT:    s_or_b64 exec, exec, s[2:3]
; GFX942-NEXT:    v_lshlrev_b16_e32 v0, 8, v12
; GFX942-NEXT:    v_lshlrev_b16_e32 v1, 8, v13
; GFX942-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX942-NEXT:    v_or_b32_sdwa v1, v10, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX942-NEXT:    v_lshlrev_b16_e32 v2, 8, v15
; GFX942-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX942-NEXT:    v_lshlrev_b16_e32 v1, 8, v14
; GFX942-NEXT:    v_or_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX942-NEXT:    v_or_b32_sdwa v2, v11, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX942-NEXT:    v_mov_b32_e32 v4, 0
; GFX942-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX942-NEXT:    global_store_dwordx2 v4, v[0:1], s[14:15]
; GFX942-NEXT:    s_endpgm
entry:
  %idx = call i32 @llvm.amdgcn.workitem.id.x()
  %gep1 = getelementptr <8 x i8>, ptr addrspace(1) %src1, i32 %idx
  %vec1 = load <8 x i8>, ptr addrspace(1) %gep1
  %gep2 = getelementptr <8 x i8>, ptr addrspace(1) %src2, i32 %idx
  %vec2 = load <8 x i8>, ptr addrspace(1) %gep2
  %cmp = icmp ult i32 %idx, 15
  br i1 %cmp, label %bb.1, label %bb.2
bb.1:
  %cmp2 = icmp ult i32 %idx, 7
  br i1 %cmp2, label %bb.2, label %bb.3

bb.2:
  %tmp5 = phi <8 x i8> [ %vec1, %entry ], [<i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, %bb.1 ]
  store <8 x i8> %tmp5, ptr addrspace(1) %dst0, align 4
  br label %bb.3

bb.3:
  %tmp7 = phi <8 x i8> [ %vec2, %bb.1], [%tmp5, %bb.2]
  store <8 x i8> %tmp7, ptr addrspace(1) %dst1, align 4
  ret void
}

define amdgpu_kernel void @v8i8_multi_block(ptr addrspace(1) %src1, ptr addrspace(1) %src2, ptr addrspace(1) nocapture %dst0, ptr addrspace(1) nocapture %dst1) {
; GFX942-LABEL: v8i8_multi_block:
; GFX942:       ; %bb.0: ; %entry
; GFX942-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x24
; GFX942-NEXT:    v_and_b32_e32 v3, 0x3ff, v0
; GFX942-NEXT:    v_lshlrev_b32_e32 v4, 3, v3
; GFX942-NEXT:    v_mov_b32_e32 v2, 0
; GFX942-NEXT:    v_cmp_gt_u32_e32 vcc, 15, v3
; GFX942-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-NEXT:    global_load_dwordx2 v[0:1], v4, s[8:9]
; GFX942-NEXT:    s_waitcnt vmcnt(0)
; GFX942-NEXT:    v_mov_b64_e32 v[6:7], v[0:1]
; GFX942-NEXT:    s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT:    s_cbranch_execz .LBB11_4
; GFX942-NEXT:  ; %bb.1: ; %bb.1
; GFX942-NEXT:    global_load_dwordx2 v[6:7], v4, s[10:11]
; GFX942-NEXT:    v_cmp_gt_u32_e32 vcc, 7, v3
; GFX942-NEXT:    s_and_saveexec_b64 s[2:3], vcc
; GFX942-NEXT:    s_cbranch_execz .LBB11_3
; GFX942-NEXT:  ; %bb.2: ; %bb.2
; GFX942-NEXT:    v_mov_b32_e32 v3, 0
; GFX942-NEXT:    global_store_dwordx2 v3, v[0:1], s[12:13]
; GFX942-NEXT:  .LBB11_3: ; %Flow
; GFX942-NEXT:    s_or_b64 exec, exec, s[2:3]
; GFX942-NEXT:  .LBB11_4: ; %bb.3
; GFX942-NEXT:    s_or_b64 exec, exec, s[0:1]
; GFX942-NEXT:    s_waitcnt vmcnt(0)
; GFX942-NEXT:    global_store_dwordx2 v2, v[6:7], s[14:15]
; GFX942-NEXT:    s_endpgm
entry:
  %idx = call i32 @llvm.amdgcn.workitem.id.x()
  %gep1 = getelementptr <8 x i8>, ptr addrspace(1) %src1, i32 %idx
  %vec1 = load <8 x i8>, ptr addrspace(1) %gep1
  %gep2 = getelementptr <8 x i8>, ptr addrspace(1) %src2, i32 %idx
  %vec2 = load <8 x i8>, ptr addrspace(1) %gep2
  %cmp = icmp ult i32 %idx, 15
  br i1 %cmp, label %bb.1, label %bb.3
bb.1:
  %cmp2 = icmp ult i32 %idx, 7
  br i1 %cmp2, label %bb.2, label %bb.3

bb.2:
  store <8 x i8> %vec1, ptr addrspace(1) %dst0, align 4
  br label %bb.3

bb.3:
  %tmp5 = phi <8 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ], [ %vec2, %bb.2]
  store <8 x i8> %tmp5, ptr addrspace(1) %dst1, align 4
  ret void
}

define amdgpu_kernel void @v32i8_loop_carried(ptr addrspace(1) %src1, ptr addrspace(1) %src2, ptr addrspace(1) nocapture %dst) {
; GFX942-LABEL: v32i8_loop_carried:
; GFX942:       ; %bb.0: ; %entry
; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX942-NEXT:    v_and_b32_e32 v1, 0x3ff, v0
; GFX942-NEXT:    v_lshlrev_b32_e32 v0, 5, v1
; GFX942-NEXT:    v_cmp_lt_u32_e32 vcc, 14, v1
; GFX942-NEXT:    s_mov_b32 s2, 0x2000604
; GFX942-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-NEXT:    global_load_dword v0, v0, s[0:1]
; GFX942-NEXT:    s_mov_b64 s[0:1], 0
; GFX942-NEXT:    s_waitcnt vmcnt(0)
; GFX942-NEXT:    v_mov_b32_e32 v1, v0
; GFX942-NEXT:  .LBB12_1: ; %bb.1
; GFX942-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX942-NEXT:    s_and_b64 s[6:7], exec, vcc
; GFX942-NEXT:    s_or_b64 s[0:1], s[6:7], s[0:1]
; GFX942-NEXT:    v_perm_b32 v1, v0, v1, s2
; GFX942-NEXT:    s_andn2_b64 exec, exec, s[0:1]
; GFX942-NEXT:    s_cbranch_execnz .LBB12_1
; GFX942-NEXT:  ; %bb.2: ; %bb.2.loopexit
; GFX942-NEXT:    s_or_b64 exec, exec, s[0:1]
; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x34
; GFX942-NEXT:    v_mov_b32_e32 v0, 0
; GFX942-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-NEXT:    global_store_dword v0, v1, s[0:1]
; GFX942-NEXT:    s_endpgm
entry:
  %idx = call i32 @llvm.amdgcn.workitem.id.x()
  %gep1 = getelementptr <32 x i8>, ptr addrspace(1) %src1, i32 %idx
  %vec1 = load <4 x i8>, ptr addrspace(1) %gep1
  br label %bb.1

bb.1:
  %temp = phi <4 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ]
  %vec2 = shufflevector <4 x i8> %vec1, <4 x i8> %temp, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
  %cmp = icmp ult i32 %idx, 15
  br i1 %cmp, label %bb.1, label %bb.2
  br label %bb.2

bb.2:
  store <4 x i8> %vec2, ptr addrspace(1) %dst, align 4
  ret void
}

; Should not have instances of "Instruction does not dominate all uses!"

define amdgpu_kernel void @v8i8_multiuse_multiblock(ptr addrspace(1) %src1, ptr addrspace(1) %src2, ptr addrspace(1) nocapture %dst1, ptr addrspace(1) nocapture %dst2, ptr addrspace(1) nocapture %dst3) {
; GFX942-LABEL: v8i8_multiuse_multiblock:
; GFX942:       ; %bb.0: ; %entry
; GFX942-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x24
; GFX942-NEXT:    v_and_b32_e32 v2, 0x3ff, v0
; GFX942-NEXT:    v_lshlrev_b32_e32 v0, 3, v2
; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x44
; GFX942-NEXT:    v_cmp_lt_u32_e64 s[2:3], 14, v2
; GFX942-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-NEXT:    global_load_dwordx2 v[0:1], v0, s[8:9]
; GFX942-NEXT:    v_cmp_gt_u32_e32 vcc, 15, v2
; GFX942-NEXT:    s_waitcnt vmcnt(0)
; GFX942-NEXT:    v_lshrrev_b32_e32 v1, 16, v0
; GFX942-NEXT:    s_and_saveexec_b64 s[4:5], vcc
; GFX942-NEXT:    s_cbranch_execz .LBB13_2
; GFX942-NEXT:  ; %bb.1: ; %bb.1
; GFX942-NEXT:    s_movk_i32 s6, 0xff00
; GFX942-NEXT:    v_mov_b32_e32 v5, 8
; GFX942-NEXT:    v_and_b32_sdwa v6, v0, s6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX942-NEXT:    s_mov_b32 s6, 0x6070504
; GFX942-NEXT:    v_cmp_gt_u32_e32 vcc, 7, v2
; GFX942-NEXT:    v_and_b32_e32 v4, 0xffffff00, v0
; GFX942-NEXT:    v_lshlrev_b16_sdwa v5, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX942-NEXT:    v_perm_b32 v7, v0, v0, s6
; GFX942-NEXT:    s_andn2_b64 s[2:3], s[2:3], exec
; GFX942-NEXT:    s_and_b64 s[6:7], vcc, exec
; GFX942-NEXT:    v_mov_b32_e32 v3, 0
; GFX942-NEXT:    v_or_b32_sdwa v4, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
; GFX942-NEXT:    v_or_b32_sdwa v5, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX942-NEXT:    v_or_b32_sdwa v6, v0, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX942-NEXT:    s_or_b64 s[2:3], s[2:3], s[6:7]
; GFX942-NEXT:    v_or_b32_sdwa v6, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX942-NEXT:    v_or_b32_sdwa v4, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX942-NEXT:    global_store_dword v3, v0, s[12:13]
; GFX942-NEXT:    global_store_dword v3, v7, s[12:13] offset:8
; GFX942-NEXT:    global_store_dword v3, v6, s[12:13] offset:16
; GFX942-NEXT:    global_store_dword v3, v4, s[12:13] offset:24
; GFX942-NEXT:  .LBB13_2: ; %Flow
; GFX942-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX942-NEXT:    s_and_saveexec_b64 s[4:5], s[2:3]
; GFX942-NEXT:    s_cbranch_execz .LBB13_4
; GFX942-NEXT:  ; %bb.3: ; %bb.2
; GFX942-NEXT:    v_lshlrev_b16_e32 v3, 8, v1
; GFX942-NEXT:    v_and_b32_e32 v4, 0xffffff00, v1
; GFX942-NEXT:    v_and_b32_e32 v5, 0xffffff00, v0
; GFX942-NEXT:    s_mov_b32 s2, 0xc0c0001
; GFX942-NEXT:    v_or_b32_sdwa v3, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX942-NEXT:    v_or_b32_sdwa v4, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX942-NEXT:    v_or_b32_sdwa v5, v1, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX942-NEXT:    v_perm_b32 v1, 0, v1, s2
; GFX942-NEXT:    v_mov_b32_e32 v2, 0
; GFX942-NEXT:    v_or_b32_sdwa v3, v4, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX942-NEXT:    v_perm_b32 v6, 0, v0, s2
; GFX942-NEXT:    s_mov_b32 s3, 0xffff0000
; GFX942-NEXT:    v_lshlrev_b32_e32 v1, 16, v1
; GFX942-NEXT:    v_and_or_b32 v7, v0, s3, v6
; GFX942-NEXT:    v_or_b32_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX942-NEXT:    v_or_b32_e32 v1, v6, v1
; GFX942-NEXT:    global_store_dword v2, v3, s[14:15]
; GFX942-NEXT:    global_store_dword v2, v4, s[14:15] offset:8
; GFX942-NEXT:    global_store_dword v2, v7, s[14:15] offset:16
; GFX942-NEXT:    global_store_dword v2, v1, s[14:15] offset:24
; GFX942-NEXT:  .LBB13_4: ; %bb.3
; GFX942-NEXT:    s_or_b64 exec, exec, s[4:5]
; GFX942-NEXT:    s_movk_i32 s3, 0xff00
; GFX942-NEXT:    v_mov_b32_e32 v4, 8
; GFX942-NEXT:    s_movk_i32 s2, 0xff
; GFX942-NEXT:    v_and_b32_sdwa v2, v0, s3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX942-NEXT:    v_lshlrev_b16_sdwa v4, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX942-NEXT:    v_or_b32_sdwa v3, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX942-NEXT:    v_or_b32_sdwa v5, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX942-NEXT:    v_lshlrev_b16_e32 v6, 8, v0
; GFX942-NEXT:    v_and_b32_sdwa v7, v0, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX942-NEXT:    v_mov_b32_e32 v1, 0
; GFX942-NEXT:    v_or_b32_sdwa v3, v5, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX942-NEXT:    v_or_b32_sdwa v7, v7, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX942-NEXT:    v_or_b32_sdwa v2, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX942-NEXT:    v_or_b32_sdwa v4, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
; GFX942-NEXT:    v_or_b32_sdwa v0, v0, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:DWORD
; GFX942-NEXT:    v_or_b32_sdwa v4, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX942-NEXT:    v_or_b32_sdwa v0, v5, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX942-NEXT:    v_or_b32_sdwa v2, v2, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX942-NEXT:    global_store_dword v1, v3, s[0:1]
; GFX942-NEXT:    global_store_dword v1, v0, s[0:1] offset:8
; GFX942-NEXT:    global_store_dword v1, v4, s[0:1] offset:16
; GFX942-NEXT:    global_store_dword v1, v2, s[0:1] offset:24
; GFX942-NEXT:    s_endpgm
entry:
  %idx = call i32 @llvm.amdgcn.workitem.id.x()
  %gep1 = getelementptr <8 x i8>, ptr addrspace(1) %src1, i32 %idx
  %vec1 = load <8 x i8>, ptr addrspace(1) %gep1
  %gep2 = getelementptr <8 x i8>, ptr addrspace(1) %src2, i32 %idx
  %vec2 = load <8 x i8>, ptr addrspace(1) %gep2
  %cmp = icmp ult i32 %idx, 15
  br i1 %cmp, label %bb.1, label %bb.2
bb.1:
  %s1 = shufflevector <8 x i8> %vec1, <8 x i8> %vec2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
  %s2 = shufflevector <8 x i8> %vec1, <8 x i8> %vec2, <4 x i32> <i32 0, i32 1, i32 3, i32 2>
  %s3 = shufflevector <8 x i8> %vec1, <8 x i8> %vec2, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
  %s4 = shufflevector <8 x i8> %vec1, <8 x i8> %vec2, <4 x i32> <i32 0, i32 2, i32 3, i32 1>
  %gep4 = getelementptr ptr addrspace(1), ptr addrspace(1) %dst1, i32 0
  %gep5 = getelementptr ptr addrspace(1), ptr addrspace(1) %dst1, i32 1
  %gep6 = getelementptr ptr addrspace(1), ptr addrspace(1) %dst1, i32 2
  %gep7 = getelementptr ptr addrspace(1), ptr addrspace(1) %dst1, i32 3
  store <4 x i8> %s1, ptr addrspace(1) %gep4, align 4
  store <4 x i8> %s2, ptr addrspace(1) %gep5, align 4
  store <4 x i8> %s3, ptr addrspace(1) %gep6, align 4
  store <4 x i8> %s4, ptr addrspace(1) %gep7, align 4
  %cmp2 = icmp ult i32 %idx, 7
  br i1 %cmp2, label %bb.2, label %bb.3

bb.2:
  %s5 = shufflevector <8 x i8> %vec1, <8 x i8> %vec2, <4 x i32> <i32 0, i32 3, i32 1, i32 2>
  %s6 = shufflevector <8 x i8> %vec1, <8 x i8> %vec2, <4 x i32> <i32 0, i32 3, i32 2, i32 1>
  %s7 = shufflevector <8 x i8> %vec1, <8 x i8> %vec2, <4 x i32> <i32 1, i32 0, i32 2, i32 3>
  %s8 = shufflevector <8 x i8> %vec1, <8 x i8> %vec2, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
  %gep8 = getelementptr ptr addrspace(1), ptr addrspace(1) %dst2, i32 0
  %gep9 = getelementptr ptr addrspace(1), ptr addrspace(1) %dst2, i32 1
  %gep10 = getelementptr ptr addrspace(1), ptr addrspace(1) %dst2, i32 2
  %gep11 = getelementptr ptr addrspace(1), ptr addrspace(1) %dst2, i32 3
  store <4 x i8> %s5, ptr addrspace(1) %gep8, align 4
  store <4 x i8> %s6, ptr addrspace(1) %gep9, align 4
  store <4 x i8> %s7, ptr addrspace(1) %gep10, align 4
  store <4 x i8> %s8, ptr addrspace(1) %gep11, align 4
  br label %bb.3

bb.3:
  %s9 = shufflevector <8 x i8> %vec1, <8 x i8> %vec2, <4 x i32> <i32 1, i32 2, i32 0, i32 3>
  %s10 = shufflevector <8 x i8> %vec1, <8 x i8> %vec2, <4 x i32> <i32 1, i32 2, i32 3, i32 0>
  %s11 = shufflevector <8 x i8> %vec1, <8 x i8> %vec2, <4 x i32> <i32 1, i32 3, i32 0, i32 2>
  %s12 = shufflevector <8 x i8> %vec1, <8 x i8> %vec2, <4 x i32> <i32 1, i32 3, i32 2, i32 0>
  %gep12 = getelementptr ptr addrspace(1), ptr addrspace(1) %dst3, i32 0
  %gep13 = getelementptr ptr addrspace(1), ptr addrspace(1) %dst3, i32 1
  %gep14 = getelementptr ptr addrspace(1), ptr addrspace(1) %dst3, i32 2
  %gep15 = getelementptr ptr addrspace(1), ptr addrspace(1) %dst3, i32 3
  store <4 x i8> %s9, ptr addrspace(1) %gep12, align 4
  store <4 x i8> %s10, ptr addrspace(1) %gep13, align 4
  store <4 x i8> %s11, ptr addrspace(1) %gep14, align 4
  store <4 x i8> %s12, ptr addrspace(1) %gep15, align 4
  ret void
}


define amdgpu_kernel void @v8i8_mfma_i8(ptr addrspace(1) %src1, ptr addrspace(1) %src2, ptr addrspace(1) nocapture %dst, ptr addrspace(1) %arg) {
; GFX942-LABEL: v8i8_mfma_i8:
; GFX942:       ; %bb.0: ; %entry
; GFX942-NEXT:    s_load_dwordx8 s[8:15], s[4:5], 0x24
; GFX942-NEXT:    v_and_b32_e32 v4, 0x3ff, v0
; GFX942-NEXT:    v_lshlrev_b32_e32 v1, 3, v4
; GFX942-NEXT:    v_mov_b32_e32 v0, 0
; GFX942-NEXT:    v_cmp_gt_u32_e32 vcc, 15, v4
; GFX942-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-NEXT:    global_load_dwordx2 v[2:3], v1, s[8:9]
; GFX942-NEXT:    s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT:    s_cbranch_execz .LBB14_2
; GFX942-NEXT:  ; %bb.1: ; %bb.1
; GFX942-NEXT:    global_load_dwordx2 v[2:3], v1, s[10:11]
; GFX942-NEXT:  .LBB14_2: ; %bb.2
; GFX942-NEXT:    s_or_b64 exec, exec, s[0:1]
; GFX942-NEXT:    s_load_dwordx4 s[0:3], s[14:15], 0x0
; GFX942-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-NEXT:    v_accvgpr_write_b32 a0, s0
; GFX942-NEXT:    v_accvgpr_write_b32 a1, s1
; GFX942-NEXT:    v_accvgpr_write_b32 a2, s2
; GFX942-NEXT:    v_accvgpr_write_b32 a3, s3
; GFX942-NEXT:    s_waitcnt vmcnt(0)
; GFX942-NEXT:    s_nop 0
; GFX942-NEXT:    v_mfma_i32_16x16x32_i8 a[0:3], v[2:3], v[2:3], a[0:3] cbsz:1 abid:2 blgp:3
; GFX942-NEXT:    s_nop 6
; GFX942-NEXT:    global_store_dwordx4 v0, a[0:3], s[12:13]
; GFX942-NEXT:    s_endpgm
entry:
  %idx = call i32 @llvm.amdgcn.workitem.id.x()
  %gep1 = getelementptr <8 x i8>, ptr addrspace(1) %src1, i32 %idx
  %vec1 = load <8 x i8>, ptr addrspace(1) %gep1
  %gep2 = getelementptr <8 x i8>, ptr addrspace(1) %src2, i32 %idx
  %vec2 = load <8 x i8>, ptr addrspace(1) %gep2
  %cmp = icmp ult i32 %idx, 15
  br i1 %cmp, label %bb.1, label %bb.2
bb.1:
  br label %bb.2

bb.2:
  %tmp5 = phi <8 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ]
  %mfmaop = bitcast <8 x i8> %tmp5 to i64
  %in.1 = load <4 x i32>, ptr addrspace(1) %arg
  %mai.1 = tail call <4 x i32> @llvm.amdgcn.mfma.i32.16x16x32.i8(i64 %mfmaop, i64 %mfmaop, <4 x i32> %in.1, i32 1, i32 2, i32 3)
  store <4 x i32> %mai.1, ptr addrspace(1) %dst, align 4
  ret void
}

; Demonstrates that even if the intrinsic is not an 8 bit intrinsic, we will still apply type coercion

define amdgpu_kernel void @v8i8_mfma_half(ptr addrspace(1) %src1, ptr addrspace(1) %src2, ptr addrspace(1) nocapture %dst, ptr addrspace(1) %arg) {
; GFX942-LABEL: v8i8_mfma_half:
; GFX942:       ; %bb.0: ; %entry
; GFX942-NEXT:    s_load_dwordx8 s[36:43], s[4:5], 0x24
; GFX942-NEXT:    v_and_b32_e32 v4, 0x3ff, v0
; GFX942-NEXT:    v_lshlrev_b32_e32 v1, 3, v4
; GFX942-NEXT:    v_mov_b32_e32 v0, 0
; GFX942-NEXT:    v_cmp_gt_u32_e32 vcc, 15, v4
; GFX942-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-NEXT:    global_load_dwordx2 v[2:3], v1, s[36:37]
; GFX942-NEXT:    s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT:    s_cbranch_execz .LBB15_2
; GFX942-NEXT:  ; %bb.1: ; %bb.1
; GFX942-NEXT:    global_load_dwordx2 v[2:3], v1, s[38:39]
; GFX942-NEXT:  .LBB15_2: ; %bb.2
; GFX942-NEXT:    s_or_b64 exec, exec, s[0:1]
; GFX942-NEXT:    s_load_dwordx16 s[16:31], s[42:43], 0x0
; GFX942-NEXT:    s_load_dwordx16 s[0:15], s[42:43], 0x40
; GFX942-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-NEXT:    v_accvgpr_write_b32 a0, s16
; GFX942-NEXT:    v_accvgpr_write_b32 a1, s17
; GFX942-NEXT:    v_accvgpr_write_b32 a2, s18
; GFX942-NEXT:    v_accvgpr_write_b32 a3, s19
; GFX942-NEXT:    v_accvgpr_write_b32 a4, s20
; GFX942-NEXT:    v_accvgpr_write_b32 a5, s21
; GFX942-NEXT:    v_accvgpr_write_b32 a6, s22
; GFX942-NEXT:    v_accvgpr_write_b32 a7, s23
; GFX942-NEXT:    v_accvgpr_write_b32 a8, s24
; GFX942-NEXT:    v_accvgpr_write_b32 a9, s25
; GFX942-NEXT:    v_accvgpr_write_b32 a10, s26
; GFX942-NEXT:    v_accvgpr_write_b32 a11, s27
; GFX942-NEXT:    v_accvgpr_write_b32 a12, s28
; GFX942-NEXT:    v_accvgpr_write_b32 a13, s29
; GFX942-NEXT:    v_accvgpr_write_b32 a14, s30
; GFX942-NEXT:    v_accvgpr_write_b32 a15, s31
; GFX942-NEXT:    v_accvgpr_write_b32 a16, s0
; GFX942-NEXT:    v_accvgpr_write_b32 a17, s1
; GFX942-NEXT:    v_accvgpr_write_b32 a18, s2
; GFX942-NEXT:    v_accvgpr_write_b32 a19, s3
; GFX942-NEXT:    v_accvgpr_write_b32 a20, s4
; GFX942-NEXT:    v_accvgpr_write_b32 a21, s5
; GFX942-NEXT:    v_accvgpr_write_b32 a22, s6
; GFX942-NEXT:    v_accvgpr_write_b32 a23, s7
; GFX942-NEXT:    v_accvgpr_write_b32 a24, s8
; GFX942-NEXT:    v_accvgpr_write_b32 a25, s9
; GFX942-NEXT:    v_accvgpr_write_b32 a26, s10
; GFX942-NEXT:    v_accvgpr_write_b32 a27, s11
; GFX942-NEXT:    v_accvgpr_write_b32 a28, s12
; GFX942-NEXT:    v_accvgpr_write_b32 a29, s13
; GFX942-NEXT:    v_accvgpr_write_b32 a30, s14
; GFX942-NEXT:    v_accvgpr_write_b32 a31, s15
; GFX942-NEXT:    s_waitcnt vmcnt(0)
; GFX942-NEXT:    s_nop 0
; GFX942-NEXT:    v_mfma_f32_32x32x4_2b_f16 a[0:31], v[2:3], v[2:3], a[0:31] cbsz:1 abid:2 blgp:3
; GFX942-NEXT:    s_nop 7
; GFX942-NEXT:    s_nop 7
; GFX942-NEXT:    s_nop 2
; GFX942-NEXT:    global_store_dwordx4 v0, a[28:31], s[40:41] offset:112
; GFX942-NEXT:    global_store_dwordx4 v0, a[24:27], s[40:41] offset:96
; GFX942-NEXT:    global_store_dwordx4 v0, a[20:23], s[40:41] offset:80
; GFX942-NEXT:    global_store_dwordx4 v0, a[16:19], s[40:41] offset:64
; GFX942-NEXT:    global_store_dwordx4 v0, a[12:15], s[40:41] offset:48
; GFX942-NEXT:    global_store_dwordx4 v0, a[8:11], s[40:41] offset:32
; GFX942-NEXT:    global_store_dwordx4 v0, a[4:7], s[40:41] offset:16
; GFX942-NEXT:    global_store_dwordx4 v0, a[0:3], s[40:41]
; GFX942-NEXT:    s_endpgm
entry:
  %idx = call i32 @llvm.amdgcn.workitem.id.x()
  %gep1 = getelementptr <8 x i8>, ptr addrspace(1) %src1, i32 %idx
  %vec1 = load <8 x i8>, ptr addrspace(1) %gep1
  %gep2 = getelementptr <8 x i8>, ptr addrspace(1) %src2, i32 %idx
  %vec2 = load <8 x i8>, ptr addrspace(1) %gep2
  %cmp = icmp ult i32 %idx, 15
  br i1 %cmp, label %bb.1, label %bb.2
bb.1:
  br label %bb.2

bb.2:
  %tmp5 = phi <8 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ]
  %mfmaop = bitcast <8 x i8> %tmp5 to <4 x half>
  %in.1 = load <32 x float>, ptr addrspace(1) %arg
  %mai.1 = tail call <32 x float> @llvm.amdgcn.mfma.f32.32x32x4f16(<4 x half> %mfmaop, <4 x half> %mfmaop, <32 x float> %in.1, i32 1, i32 2, i32 3)
  store <32 x float> %mai.1, ptr addrspace(1) %dst, align 4
  ret void
}


define amdgpu_kernel void @v8i8_intrinsic(ptr addrspace(1) %src1, ptr addrspace(1) %src2, ptr addrspace(1) nocapture %dst) {
; GFX942-LABEL: v8i8_intrinsic:
; GFX942:       ; %bb.0: ; %entry
; GFX942-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX942-NEXT:    s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX942-NEXT:    v_and_b32_e32 v4, 0x3ff, v0
; GFX942-NEXT:    v_lshlrev_b32_e32 v3, 3, v4
; GFX942-NEXT:    v_mov_b32_e32 v2, 0
; GFX942-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-NEXT:    global_load_dwordx2 v[0:1], v3, s[0:1]
; GFX942-NEXT:    v_cmp_gt_u32_e32 vcc, 15, v4
; GFX942-NEXT:    s_and_saveexec_b64 s[0:1], vcc
; GFX942-NEXT:    s_cbranch_execz .LBB16_2
; GFX942-NEXT:  ; %bb.1: ; %bb.1
; GFX942-NEXT:    global_load_dwordx2 v[0:1], v3, s[2:3]
; GFX942-NEXT:  .LBB16_2: ; %bb.2
; GFX942-NEXT:    s_or_b64 exec, exec, s[0:1]
; GFX942-NEXT:    s_waitcnt vmcnt(0)
; GFX942-NEXT:    v_pk_fma_f32 v[0:1], v[0:1], v[0:1], v[0:1]
; GFX942-NEXT:    global_store_dwordx2 v2, v[0:1], s[6:7]
; GFX942-NEXT:    s_endpgm
entry:
  %idx = call i32 @llvm.amdgcn.workitem.id.x()
  %gep1 = getelementptr <8 x i8>, ptr addrspace(1) %src1, i32 %idx
  %vec1 = load <8 x i8>, ptr addrspace(1) %gep1
  %gep2 = getelementptr <8 x i8>, ptr addrspace(1) %src2, i32 %idx
  %vec2 = load <8 x i8>, ptr addrspace(1) %gep2
  %cmp = icmp ult i32 %idx, 15
  br i1 %cmp, label %bb.1, label %bb.2
bb.1:
  br label %bb.2

bb.2:
  %tmp5 = phi <8 x i8> [ %vec1, %entry ], [ %vec2, %bb.1 ]
  %op = bitcast <8 x i8> %tmp5 to <2 x float>
  %result = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %op, <2 x float> %op, <2 x float> %op)
  store <2 x float> %result, ptr addrspace(1) %dst, align 8
  ret void
}

declare i32 @llvm.amdgcn.workitem.id.x()