# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -simplify-mir -run-pass=si-peephole-sdwa -o - %s | FileCheck %s

# Test the combination of SDWA selections in si-peephole-sdwa. In each
# example, the SDWA destination selection specified on the first instruction
# must be combined with the destination selection that the pass determines
# for the operand, i.e. the second instruction.  In the cases where
# this is not possible, no conversion should occur.

---
name: op_select_word_1_instr_select_dword
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: op_select_word_1_instr_select_dword
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 5, 0, 0, 0, implicit $exec
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0
    %1:vgpr_32 = COPY $vgpr0
    %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 6, 0, 0, 0, implicit $exec
    %3:vgpr_32 = V_LSHLREV_B32_e32  16, %2,  implicit $exec /* Select WORD_1 */
    %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec

    S_ENDPGM 0
...

---
name: op_select_word_1_instr_select_word_1
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: op_select_word_1_instr_select_word_1
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 5, 0, 0, 0, implicit $exec
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0
    %1:vgpr_32 = COPY $vgpr0
    %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 5, 0, 0, 0, implicit $exec
    %3:vgpr_32 = V_LSHLREV_B32_e32  16, %2,  implicit $exec /* Select WORD_1 */
    %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec

    S_ENDPGM 0
...

---
name: op_select_word_1_instr_select_word_0
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: op_select_word_1_instr_select_word_0
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 5, 0, 0, 0, implicit $exec
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0
    %1:vgpr_32 = COPY $vgpr0
    %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 4, 0, 0, 0, implicit $exec
    %3:vgpr_32 = V_LSHLREV_B32_e32  16, %2,  implicit $exec /* Select WORD_1 */
    %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec

    S_ENDPGM 0
...

---
name: op_select_word_1_instr_select_byte_3
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: op_select_word_1_instr_select_byte_3
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 3, 0, 0, 0, implicit $exec
    ; CHECK-NEXT: [[V_LSHLREV_B32_e32_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 16, [[V_LSHRREV_B32_sdwa]], implicit $exec
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0
    %1:vgpr_32 = COPY $vgpr0
    %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 3, 0, 0, 0, implicit $exec
    %3:vgpr_32 = V_LSHLREV_B32_e32  16, %2,  implicit $exec /* Select WORD_1 */
    %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec

    S_ENDPGM 0
...

---
name: op_select_word_1_instr_select_byte_2
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: op_select_word_1_instr_select_byte_2
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 0, 0, implicit $exec
    ; CHECK-NEXT: [[V_LSHLREV_B32_e32_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 16, [[V_LSHRREV_B32_sdwa]], implicit $exec
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0
    %1:vgpr_32 = COPY $vgpr0
    %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 0, 0, implicit $exec
    %3:vgpr_32 = V_LSHLREV_B32_e32  16, %2,  implicit $exec /* Select WORD_1 */
    %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec

    S_ENDPGM 0
...

---
name: op_select_word_1_instr_select_byte_1
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: op_select_word_1_instr_select_byte_1
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 3, 0, 0, 0, implicit $exec
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0
    %1:vgpr_32 = COPY $vgpr0
    %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 1, 0, 0, 0, implicit $exec
    %3:vgpr_32 = V_LSHLREV_B32_e32  16, %2,  implicit $exec /* Select WORD_1 */
    %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec

    S_ENDPGM 0
...

---
name: op_select_word_1_instr_select_byte_0
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: op_select_word_1_instr_select_byte_0
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 0, 0, implicit $exec
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0
    %1:vgpr_32 = COPY $vgpr0
    %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 0, 0, 0, 0, implicit $exec
    %3:vgpr_32 = V_LSHLREV_B32_e32  16, %2,  implicit $exec /* Select WORD_1 */
    %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec

    S_ENDPGM 0
...

---
name: op_select_byte_3_instr_select_dword
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: op_select_byte_3_instr_select_dword
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 3, 0, 0, 0, implicit $exec
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0
    %1:vgpr_32 = COPY $vgpr0
    %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 6, 0, 0, 0, implicit $exec
    %3:vgpr_32 = V_LSHLREV_B32_e32  24, %2,  implicit $exec /* Select BYTE_3 */
    %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec

    S_ENDPGM 0
...

---
name: op_select_byte_3_instr_select_word_1
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: op_select_byte_3_instr_select_word_1
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 5, 0, 0, 0, implicit $exec
    ; CHECK-NEXT: [[V_LSHLREV_B32_e32_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 24, [[V_LSHRREV_B32_sdwa]], implicit $exec
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0
    %1:vgpr_32 = COPY $vgpr0
    %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 5, 0, 0, 0, implicit $exec
    %3:vgpr_32 = V_LSHLREV_B32_e32  24, %2,  implicit $exec /* Select BYTE_3 */
    %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec

    S_ENDPGM 0
...

---
name: op_select_byte_3_instr_select_word_0
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: op_select_byte_3_instr_select_word_0
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 4, 0, 0, 0, implicit $exec
    ; CHECK-NEXT: [[V_LSHLREV_B32_e32_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 24, [[V_LSHRREV_B32_sdwa]], implicit $exec
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0
    %1:vgpr_32 = COPY $vgpr0
    %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 4, 0, 0, 0, implicit $exec
    %3:vgpr_32 = V_LSHLREV_B32_e32  24, %2,  implicit $exec /* Select BYTE_3 */
    %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec

    S_ENDPGM 0
...

---
name: op_select_byte_3_instr_select_byte_3
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: op_select_byte_3_instr_select_byte_3
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 3, 0, 0, 0, implicit $exec
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0
    %1:vgpr_32 = COPY $vgpr0
    %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 3, 0, 0, 0, implicit $exec
    %3:vgpr_32 = V_LSHLREV_B32_e32  24, %2,  implicit $exec /* Select BYTE_3 */
    %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec

    S_ENDPGM 0
...

---
name: op_select_byte_3_instr_select_byte_2
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: op_select_byte_3_instr_select_byte_2
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 0, 0, implicit $exec
    ; CHECK-NEXT: [[V_LSHLREV_B32_e32_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 24, [[V_LSHRREV_B32_sdwa]], implicit $exec
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0
    %1:vgpr_32 = COPY $vgpr0
    %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 0, 0, implicit $exec
    %3:vgpr_32 = V_LSHLREV_B32_e32  24, %2,  implicit $exec /* Select BYTE_3 */
    %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec

    S_ENDPGM 0
...

---
name: op_select_byte_3_instr_select_byte_1
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: op_select_byte_3_instr_select_byte_1
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 1, 0, 0, 0, implicit $exec
    ; CHECK-NEXT: [[V_LSHLREV_B32_e32_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 24, [[V_LSHRREV_B32_sdwa]], implicit $exec
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0
    %1:vgpr_32 = COPY $vgpr0
    %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 1, 0, 0, 0, implicit $exec
    %3:vgpr_32 = V_LSHLREV_B32_e32  24, %2,  implicit $exec /* Select BYTE_3 */
    %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec

    S_ENDPGM 0
...

---
name: op_select_byte_3_instr_select_byte_0
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0
    ; CHECK-LABEL: name: op_select_byte_3_instr_select_byte_0
    ; CHECK: liveins: $vgpr0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 0, 0, 0, 0, implicit $exec
    ; CHECK-NEXT: [[V_LSHLREV_B32_e32_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e32 24, [[V_LSHRREV_B32_sdwa]], implicit $exec
    ; CHECK-NEXT: [[V_LSHRREV_B32_sdwa1:%[0-9]+]]:vgpr_32 = V_LSHRREV_B32_sdwa 0, [[COPY]], 0, [[COPY]], 0, 2, 0, 6, 6, implicit $exec
    ; CHECK-NEXT: S_ENDPGM 0
    %1:vgpr_32 = COPY $vgpr0
    %2:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 0, 0, 0, 0, implicit $exec
    %3:vgpr_32 = V_LSHLREV_B32_e32  24, %2,  implicit $exec /* Select BYTE_3 */
    %4:vgpr_32 = V_LSHRREV_B32_sdwa 0, %1, 0, %1, 0, 2, 0, 6, 6, implicit $exec

    S_ENDPGM 0
...