; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn--amdhsa < %s | FileCheck -check-prefix=GCN %s

; Effectively, check that the compile finishes; in the case
; of an infinite loop, llc toggles between merging 2 ST4s
; ( MergeConsecutiveStores() ) and breaking the resulting ST8
; apart ( LegalizeStoreOps() ).

define amdgpu_kernel void @_Z6brokenPd(ptr %arg) {
; GCN-LABEL: _Z6brokenPd:
; GCN:       ; %bb.0: ; %bb
; GCN-NEXT:    s_mov_b32 flat_scratch_lo, s13
; GCN-NEXT:    s_add_i32 s12, s12, s17
; GCN-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 8
; GCN-NEXT:    s_add_u32 s0, s0, s17
; GCN-NEXT:    s_addc_u32 s1, s1, 0
; GCN-NEXT:    s_load_dwordx2 s[4:5], s[8:9], 0x0
; GCN-NEXT:    v_mov_b32_e32 v2, 0
; GCN-NEXT:    v_mov_b32_e32 v3, 0x7ff80000
; GCN-NEXT:    s_waitcnt lgkmcnt(0)
; GCN-NEXT:    v_mov_b32_e32 v0, s4
; GCN-NEXT:    v_mov_b32_e32 v1, s5
; GCN-NEXT:    s_add_u32 s4, s4, 4
; GCN-NEXT:    s_addc_u32 s5, s5, 0
; GCN-NEXT:    flat_store_dword v[0:1], v2
; GCN-NEXT:    v_mov_b32_e32 v0, s4
; GCN-NEXT:    v_mov_b32_e32 v1, s5
; GCN-NEXT:    flat_store_dword v[0:1], v3
; GCN-NEXT:    s_endpgm
bb:
  %tmp = alloca double, align 8, addrspace(5)
  %tmp1 = alloca double, align 8, addrspace(5)
  %tmp2 = load double, ptr %arg, align 8
  br i1 1, label %bb6, label %bb4

bb3:                                             ; No predecessors!
  br label %bb4

bb4:                                             ; preds = %bb3, %bb
  %tmp5 = phi ptr addrspace(5) [ %tmp1, %bb3 ], [ %tmp, %bb ]
  store double %tmp2, ptr addrspace(5) %tmp5, align 8
  br label %bb6

bb6:                                             ; preds = %bb4, %bb
  %tmp7 = phi double [ 0x7FF8123000000000, %bb4 ], [ 0x7FF8000000000000, %bb ]
  store double %tmp7, ptr %arg, align 8
  ret void
}