; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=+architected-sgprs < %s | FileCheck -check-prefix=GFX9-SDAG %s ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -mattr=+architected-sgprs -global-isel < %s | FileCheck -check-prefix=GFX9-GISEL %s ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 < %s | FileCheck -check-prefix=GFX12-SDAG %s ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -global-isel < %s | FileCheck -check-prefix=GFX12-GISEL %s ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1250 < %s | FileCheck -check-prefix=GFX1250-SDAG %s ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1250 -global-isel < %s | FileCheck -check-prefix=GFX1250-GISEL %s define amdgpu_cs void @_amdgpu_cs_main() { ; GFX9-SDAG-LABEL: _amdgpu_cs_main: ; GFX9-SDAG: ; %bb.0: ; %.entry ; GFX9-SDAG-NEXT: s_lshr_b32 s0, ttmp7, 16 ; GFX9-SDAG-NEXT: s_and_b32 s1, ttmp7, 0xffff ; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, ttmp9 ; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s0 ; GFX9-SDAG-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0 ; GFX9-SDAG-NEXT: s_endpgm ; ; GFX9-GISEL-LABEL: _amdgpu_cs_main: ; GFX9-GISEL: ; %bb.0: ; %.entry ; GFX9-GISEL-NEXT: s_mov_b32 s0, ttmp9 ; GFX9-GISEL-NEXT: s_and_b32 s1, ttmp7, 0xffff ; GFX9-GISEL-NEXT: s_lshr_b32 s2, ttmp7, 16 ; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-GISEL-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0 ; GFX9-GISEL-NEXT: s_endpgm ; ; GFX12-SDAG-LABEL: _amdgpu_cs_main: ; GFX12-SDAG: ; %bb.0: ; %.entry ; GFX12-SDAG-NEXT: s_and_b32 s0, ttmp7, 0xffff ; GFX12-SDAG-NEXT: s_lshr_b32 s1, ttmp7, 16 ; GFX12-SDAG-NEXT: v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, s0 ; GFX12-SDAG-NEXT: v_mov_b32_e32 v2, s1 ; GFX12-SDAG-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null ; GFX12-SDAG-NEXT: s_endpgm ; ; GFX12-GISEL-LABEL: _amdgpu_cs_main: ; GFX12-GISEL: ; %bb.0: ; %.entry ; GFX12-GISEL-NEXT: s_mov_b32 s0, ttmp9 ; GFX12-GISEL-NEXT: s_and_b32 s1, ttmp7, 0xffff ; GFX12-GISEL-NEXT: s_lshr_b32 s2, ttmp7, 16 ; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GFX12-GISEL-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null ; GFX12-GISEL-NEXT: s_endpgm ; ; GFX1250-SDAG-LABEL: _amdgpu_cs_main: ; GFX1250-SDAG: ; %bb.0: ; %.entry ; GFX1250-SDAG-NEXT: s_bfe_u32 s0, ttmp6, 0x4000c ; GFX1250-SDAG-NEXT: s_bfe_u32 s2, ttmp6, 0x40010 ; GFX1250-SDAG-NEXT: s_add_co_i32 s0, s0, 1 ; GFX1250-SDAG-NEXT: s_and_b32 s1, ttmp6, 15 ; GFX1250-SDAG-NEXT: s_mul_i32 s0, ttmp9, s0 ; GFX1250-SDAG-NEXT: s_and_b32 s3, ttmp7, 0xffff ; GFX1250-SDAG-NEXT: s_add_co_i32 s2, s2, 1 ; GFX1250-SDAG-NEXT: s_bfe_u32 s4, ttmp6, 0x40014 ; GFX1250-SDAG-NEXT: s_add_co_i32 s1, s1, s0 ; GFX1250-SDAG-NEXT: s_mul_i32 s0, s3, s2 ; GFX1250-SDAG-NEXT: s_bfe_u32 s2, ttmp6, 0x40004 ; GFX1250-SDAG-NEXT: s_lshr_b32 s5, ttmp7, 16 ; GFX1250-SDAG-NEXT: s_add_co_i32 s4, s4, 1 ; GFX1250-SDAG-NEXT: s_add_co_i32 s2, s2, s0 ; GFX1250-SDAG-NEXT: s_mul_i32 s0, s5, s4 ; GFX1250-SDAG-NEXT: s_bfe_u32 s4, ttmp6, 0x40008 ; GFX1250-SDAG-NEXT: s_getreg_b32 s6, hwreg(HW_REG_IB_STS2, 6, 4) ; GFX1250-SDAG-NEXT: s_add_co_i32 s4, s4, s0 ; GFX1250-SDAG-NEXT: s_cmp_eq_u32 s6, 0 ; GFX1250-SDAG-NEXT: s_cselect_b32 s0, s5, s4 ; GFX1250-SDAG-NEXT: s_cselect_b32 s1, ttmp9, s1 ; GFX1250-SDAG-NEXT: s_cselect_b32 s2, s3, s2 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s2 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, s0 ; GFX1250-SDAG-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null ; GFX1250-SDAG-NEXT: s_endpgm ; ; GFX1250-GISEL-LABEL: _amdgpu_cs_main: ; GFX1250-GISEL: ; %bb.0: ; %.entry ; GFX1250-GISEL-NEXT: s_bfe_u32 s0, ttmp6, 0x4000c ; GFX1250-GISEL-NEXT: s_and_b32 s1, ttmp6, 15 ; GFX1250-GISEL-NEXT: s_add_co_i32 s0, s0, 1 ; GFX1250-GISEL-NEXT: s_getreg_b32 s2, hwreg(HW_REG_IB_STS2, 6, 4) ; GFX1250-GISEL-NEXT: s_mul_i32 s0, ttmp9, s0 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-GISEL-NEXT: s_add_co_i32 s1, s1, s0 ; GFX1250-GISEL-NEXT: s_cmp_eq_u32 s2, 0 ; GFX1250-GISEL-NEXT: s_cselect_b32 s0, ttmp9, s1 ; GFX1250-GISEL-NEXT: s_bfe_u32 s1, ttmp6, 0x40010 ; GFX1250-GISEL-NEXT: s_and_b32 s3, ttmp7, 0xffff ; GFX1250-GISEL-NEXT: s_add_co_i32 s1, s1, 1 ; GFX1250-GISEL-NEXT: s_bfe_u32 s4, ttmp6, 0x40004 ; GFX1250-GISEL-NEXT: s_mul_i32 s1, s3, s1 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-GISEL-NEXT: s_add_co_i32 s4, s4, s1 ; GFX1250-GISEL-NEXT: s_cmp_eq_u32 s2, 0 ; GFX1250-GISEL-NEXT: s_cselect_b32 s1, s3, s4 ; GFX1250-GISEL-NEXT: s_bfe_u32 s3, ttmp6, 0x40014 ; GFX1250-GISEL-NEXT: s_lshr_b32 s4, ttmp7, 16 ; GFX1250-GISEL-NEXT: s_add_co_i32 s3, s3, 1 ; GFX1250-GISEL-NEXT: s_bfe_u32 s5, ttmp6, 0x40008 ; GFX1250-GISEL-NEXT: s_mul_i32 s3, s4, s3 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-GISEL-NEXT: s_add_co_i32 s5, s5, s3 ; GFX1250-GISEL-NEXT: s_cmp_eq_u32 s2, 0 ; GFX1250-GISEL-NEXT: s_cselect_b32 s2, s4, s5 ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GFX1250-GISEL-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null ; GFX1250-GISEL-NEXT: s_endpgm .entry: %idx = call i32 @llvm.amdgcn.workgroup.id.x() %idy = call i32 @llvm.amdgcn.workgroup.id.y() %idz = call i32 @llvm.amdgcn.workgroup.id.z() %ielemx = insertelement <3 x i32> undef, i32 %idx, i64 0 %ielemy = insertelement <3 x i32> %ielemx, i32 %idy, i64 1 %ielemz = insertelement <3 x i32> %ielemy, i32 %idz, i64 2 call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> %ielemz, ptr addrspace(8) undef, i32 0, i32 0, i32 0) ret void } define amdgpu_cs void @workgroup_id_no_clusters() "amdgpu-cluster-dims"="0,0,0" { ; GFX9-SDAG-LABEL: workgroup_id_no_clusters: ; GFX9-SDAG: ; %bb.0: ; %.entry ; GFX9-SDAG-NEXT: s_lshr_b32 s0, ttmp7, 16 ; GFX9-SDAG-NEXT: s_and_b32 s1, ttmp7, 0xffff ; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, ttmp9 ; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s0 ; GFX9-SDAG-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0 ; GFX9-SDAG-NEXT: s_endpgm ; ; GFX9-GISEL-LABEL: workgroup_id_no_clusters: ; GFX9-GISEL: ; %bb.0: ; %.entry ; GFX9-GISEL-NEXT: s_mov_b32 s0, ttmp9 ; GFX9-GISEL-NEXT: s_and_b32 s1, ttmp7, 0xffff ; GFX9-GISEL-NEXT: s_lshr_b32 s2, ttmp7, 16 ; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-GISEL-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0 ; GFX9-GISEL-NEXT: s_endpgm ; ; GFX12-SDAG-LABEL: workgroup_id_no_clusters: ; GFX12-SDAG: ; %bb.0: ; %.entry ; GFX12-SDAG-NEXT: s_and_b32 s0, ttmp7, 0xffff ; GFX12-SDAG-NEXT: s_lshr_b32 s1, ttmp7, 16 ; GFX12-SDAG-NEXT: v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, s0 ; GFX12-SDAG-NEXT: v_mov_b32_e32 v2, s1 ; GFX12-SDAG-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null ; GFX12-SDAG-NEXT: s_endpgm ; ; GFX12-GISEL-LABEL: workgroup_id_no_clusters: ; GFX12-GISEL: ; %bb.0: ; %.entry ; GFX12-GISEL-NEXT: s_mov_b32 s0, ttmp9 ; GFX12-GISEL-NEXT: s_and_b32 s1, ttmp7, 0xffff ; GFX12-GISEL-NEXT: s_lshr_b32 s2, ttmp7, 16 ; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GFX12-GISEL-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null ; GFX12-GISEL-NEXT: s_endpgm ; ; GFX1250-SDAG-LABEL: workgroup_id_no_clusters: ; GFX1250-SDAG: ; %bb.0: ; %.entry ; GFX1250-SDAG-NEXT: s_and_b32 s0, ttmp7, 0xffff ; GFX1250-SDAG-NEXT: s_lshr_b32 s1, ttmp7, 16 ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, s0 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, s1 ; GFX1250-SDAG-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null ; GFX1250-SDAG-NEXT: s_endpgm ; ; GFX1250-GISEL-LABEL: workgroup_id_no_clusters: ; GFX1250-GISEL: ; %bb.0: ; %.entry ; GFX1250-GISEL-NEXT: s_mov_b32 s0, ttmp9 ; GFX1250-GISEL-NEXT: s_and_b32 s1, ttmp7, 0xffff ; GFX1250-GISEL-NEXT: s_lshr_b32 s2, ttmp7, 16 ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GFX1250-GISEL-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null ; GFX1250-GISEL-NEXT: s_endpgm .entry: %idx = call i32 @llvm.amdgcn.workgroup.id.x() %idy = call i32 @llvm.amdgcn.workgroup.id.y() %idz = call i32 @llvm.amdgcn.workgroup.id.z() %ielemx = insertelement <3 x i32> undef, i32 %idx, i64 0 %ielemy = insertelement <3 x i32> %ielemx, i32 %idy, i64 1 %ielemz = insertelement <3 x i32> %ielemy, i32 %idz, i64 2 call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> %ielemz, ptr addrspace(8) undef, i32 0, i32 0, i32 0) ret void } define amdgpu_cs void @workgroup_id_optimized() "amdgpu-cluster-dims"="2,3,4" { ; GFX9-SDAG-LABEL: workgroup_id_optimized: ; GFX9-SDAG: ; %bb.0: ; %.entry ; GFX9-SDAG-NEXT: s_lshr_b32 s0, ttmp7, 16 ; GFX9-SDAG-NEXT: s_and_b32 s1, ttmp7, 0xffff ; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, ttmp9 ; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s0 ; GFX9-SDAG-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0 ; GFX9-SDAG-NEXT: s_endpgm ; ; GFX9-GISEL-LABEL: workgroup_id_optimized: ; GFX9-GISEL: ; %bb.0: ; %.entry ; GFX9-GISEL-NEXT: s_mov_b32 s0, ttmp9 ; GFX9-GISEL-NEXT: s_and_b32 s1, ttmp7, 0xffff ; GFX9-GISEL-NEXT: s_lshr_b32 s2, ttmp7, 16 ; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-GISEL-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0 ; GFX9-GISEL-NEXT: s_endpgm ; ; GFX12-SDAG-LABEL: workgroup_id_optimized: ; GFX12-SDAG: ; %bb.0: ; %.entry ; GFX12-SDAG-NEXT: s_and_b32 s0, ttmp7, 0xffff ; GFX12-SDAG-NEXT: s_lshr_b32 s1, ttmp7, 16 ; GFX12-SDAG-NEXT: v_dual_mov_b32 v0, ttmp9 :: v_dual_mov_b32 v1, s0 ; GFX12-SDAG-NEXT: v_mov_b32_e32 v2, s1 ; GFX12-SDAG-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null ; GFX12-SDAG-NEXT: s_endpgm ; ; GFX12-GISEL-LABEL: workgroup_id_optimized: ; GFX12-GISEL: ; %bb.0: ; %.entry ; GFX12-GISEL-NEXT: s_mov_b32 s0, ttmp9 ; GFX12-GISEL-NEXT: s_and_b32 s1, ttmp7, 0xffff ; GFX12-GISEL-NEXT: s_lshr_b32 s2, ttmp7, 16 ; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GFX12-GISEL-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null ; GFX12-GISEL-NEXT: s_endpgm ; ; GFX1250-SDAG-LABEL: workgroup_id_optimized: ; GFX1250-SDAG: ; %bb.0: ; %.entry ; GFX1250-SDAG-NEXT: s_lshl_b32 s0, ttmp9, 1 ; GFX1250-SDAG-NEXT: s_and_b32 s1, ttmp6, 15 ; GFX1250-SDAG-NEXT: s_lshr_b32 s2, ttmp7, 14 ; GFX1250-SDAG-NEXT: s_add_co_i32 s1, s1, s0 ; GFX1250-SDAG-NEXT: s_and_b32 s0, s2, 0x3fffc ; GFX1250-SDAG-NEXT: s_and_b32 s2, ttmp7, 0xffff ; GFX1250-SDAG-NEXT: s_bfe_u32 s3, ttmp6, 0x40008 ; GFX1250-SDAG-NEXT: s_mul_i32 s2, s2, 3 ; GFX1250-SDAG-NEXT: s_bfe_u32 s4, ttmp6, 0x40004 ; GFX1250-SDAG-NEXT: s_add_co_i32 s3, s3, s0 ; GFX1250-SDAG-NEXT: s_add_co_i32 s4, s4, s2 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s4 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v2, s3 ; GFX1250-SDAG-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null ; GFX1250-SDAG-NEXT: s_endpgm ; ; GFX1250-GISEL-LABEL: workgroup_id_optimized: ; GFX1250-GISEL: ; %bb.0: ; %.entry ; GFX1250-GISEL-NEXT: s_and_b32 s1, ttmp7, 0xffff ; GFX1250-GISEL-NEXT: s_and_b32 s0, ttmp6, 15 ; GFX1250-GISEL-NEXT: s_bfe_u32 s2, ttmp6, 0x40004 ; GFX1250-GISEL-NEXT: s_mul_i32 s1, s1, 3 ; GFX1250-GISEL-NEXT: s_lshr_b32 s3, ttmp7, 16 ; GFX1250-GISEL-NEXT: s_bfe_u32 s4, ttmp6, 0x40008 ; GFX1250-GISEL-NEXT: s_lshl1_add_u32 s0, ttmp9, s0 ; GFX1250-GISEL-NEXT: s_add_co_i32 s1, s2, s1 ; GFX1250-GISEL-NEXT: s_lshl2_add_u32 s2, s3, s4 ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, s2 ; GFX1250-GISEL-NEXT: buffer_store_b96 v[0:2], off, s[0:3], null ; GFX1250-GISEL-NEXT: s_endpgm .entry: %idx = call i32 @llvm.amdgcn.workgroup.id.x() %idy = call i32 @llvm.amdgcn.workgroup.id.y() %idz = call i32 @llvm.amdgcn.workgroup.id.z() %ielemx = insertelement <3 x i32> undef, i32 %idx, i64 0 %ielemy = insertelement <3 x i32> %ielemx, i32 %idy, i64 1 %ielemz = insertelement <3 x i32> %ielemy, i32 %idz, i64 2 call void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32> %ielemz, ptr addrspace(8) undef, i32 0, i32 0, i32 0) ret void } define amdgpu_cs void @caller() { ; GFX9-SDAG-LABEL: caller: ; GFX9-SDAG: ; %bb.0: ; GFX9-SDAG-NEXT: s_getpc_b64 s[8:9] ; GFX9-SDAG-NEXT: s_mov_b32 s8, s0 ; GFX9-SDAG-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x10 ; GFX9-SDAG-NEXT: s_mov_b32 s5, callee@abs32@hi ; GFX9-SDAG-NEXT: s_mov_b32 s4, callee@abs32@lo ; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, ttmp9 ; GFX9-SDAG-NEXT: s_mov_b32 s32, 0 ; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-SDAG-NEXT: s_add_u32 s8, s8, s0 ; GFX9-SDAG-NEXT: s_addc_u32 s9, s9, 0 ; GFX9-SDAG-NEXT: s_mov_b64 s[0:1], s[8:9] ; GFX9-SDAG-NEXT: s_mov_b64 s[2:3], s[10:11] ; GFX9-SDAG-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX9-SDAG-NEXT: s_endpgm ; ; GFX9-GISEL-LABEL: caller: ; GFX9-GISEL: ; %bb.0: ; GFX9-GISEL-NEXT: s_getpc_b64 s[8:9] ; GFX9-GISEL-NEXT: s_mov_b32 s8, s0 ; GFX9-GISEL-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x10 ; GFX9-GISEL-NEXT: s_mov_b32 s4, callee@abs32@lo ; GFX9-GISEL-NEXT: s_mov_b32 s5, callee@abs32@hi ; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, ttmp9 ; GFX9-GISEL-NEXT: s_mov_b32 s32, 0 ; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-GISEL-NEXT: s_add_u32 s8, s8, s0 ; GFX9-GISEL-NEXT: s_addc_u32 s9, s9, 0 ; GFX9-GISEL-NEXT: s_mov_b64 s[0:1], s[8:9] ; GFX9-GISEL-NEXT: s_mov_b64 s[2:3], s[10:11] ; GFX9-GISEL-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX9-GISEL-NEXT: s_endpgm ; ; GFX12-SDAG-LABEL: caller: ; GFX12-SDAG: ; %bb.0: ; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, ttmp9 ; GFX12-SDAG-NEXT: s_mov_b32 s1, callee@abs32@hi ; GFX12-SDAG-NEXT: s_mov_b32 s0, callee@abs32@lo ; GFX12-SDAG-NEXT: s_mov_b32 s32, 0 ; GFX12-SDAG-NEXT: s_wait_alu 0xfffe ; GFX12-SDAG-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX12-SDAG-NEXT: s_endpgm ; ; GFX12-GISEL-LABEL: caller: ; GFX12-GISEL: ; %bb.0: ; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, ttmp9 ; GFX12-GISEL-NEXT: s_mov_b32 s0, callee@abs32@lo ; GFX12-GISEL-NEXT: s_mov_b32 s1, callee@abs32@hi ; GFX12-GISEL-NEXT: s_mov_b32 s32, 0 ; GFX12-GISEL-NEXT: s_wait_alu 0xfffe ; GFX12-GISEL-NEXT: s_swappc_b64 s[30:31], s[0:1] ; GFX12-GISEL-NEXT: s_endpgm ; ; GFX1250-SDAG-LABEL: caller: ; GFX1250-SDAG: ; %bb.0: ; GFX1250-SDAG-NEXT: s_bfe_u32 s0, ttmp6, 0x4000c ; GFX1250-SDAG-NEXT: s_and_b32 s1, ttmp6, 15 ; GFX1250-SDAG-NEXT: s_add_co_i32 s0, s0, 1 ; GFX1250-SDAG-NEXT: s_getreg_b32 s2, hwreg(HW_REG_IB_STS2, 6, 4) ; GFX1250-SDAG-NEXT: s_mul_i32 s0, ttmp9, s0 ; GFX1250-SDAG-NEXT: s_mov_b32 s32, 0 ; GFX1250-SDAG-NEXT: s_add_co_i32 s1, s1, s0 ; GFX1250-SDAG-NEXT: s_cmp_eq_u32 s2, 0 ; GFX1250-SDAG-NEXT: s_cselect_b32 s2, ttmp9, s1 ; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], callee@abs64 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v0, s2 ; GFX1250-SDAG-NEXT: s_swap_pc_i64 s[30:31], s[0:1] ; GFX1250-SDAG-NEXT: s_endpgm ; ; GFX1250-GISEL-LABEL: caller: ; GFX1250-GISEL: ; %bb.0: ; GFX1250-GISEL-NEXT: s_bfe_u32 s0, ttmp6, 0x4000c ; GFX1250-GISEL-NEXT: s_and_b32 s1, ttmp6, 15 ; GFX1250-GISEL-NEXT: s_add_co_i32 s0, s0, 1 ; GFX1250-GISEL-NEXT: s_getreg_b32 s2, hwreg(HW_REG_IB_STS2, 6, 4) ; GFX1250-GISEL-NEXT: s_mul_i32 s0, ttmp9, s0 ; GFX1250-GISEL-NEXT: s_mov_b32 s32, 0 ; GFX1250-GISEL-NEXT: s_add_co_i32 s1, s1, s0 ; GFX1250-GISEL-NEXT: s_cmp_eq_u32 s2, 0 ; GFX1250-GISEL-NEXT: s_cselect_b32 s2, ttmp9, s1 ; GFX1250-GISEL-NEXT: s_mov_b64 s[0:1], callee@abs64 ; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, s2 ; GFX1250-GISEL-NEXT: s_swap_pc_i64 s[30:31], s[0:1] ; GFX1250-GISEL-NEXT: s_endpgm %idx = call i32 @llvm.amdgcn.workgroup.id.x() call amdgpu_gfx void @callee(i32 %idx) ret void } declare amdgpu_gfx void @callee(i32) declare i32 @llvm.amdgcn.workgroup.id.x() declare i32 @llvm.amdgcn.workgroup.id.y() declare i32 @llvm.amdgcn.workgroup.id.z() declare void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32>, ptr addrspace(8), i32, i32, i32 immarg)