; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX10PLUS-GISE %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX10PLUS %s
; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12-GISE %s
; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GFX12 %s

define amdgpu_ps void @atomic_swap_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
; GFX10PLUS-GISE-LABEL: atomic_swap_1d:
; GFX10PLUS-GISE:       ; %bb.0:
; GFX10PLUS-GISE-NEXT:    image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-GISE-NEXT:    s_endpgm
;
; GFX10PLUS-LABEL: atomic_swap_1d:
; GFX10PLUS:       ; %bb.0:
; GFX10PLUS-NEXT:    image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-NEXT:    s_endpgm
;
; GFX12-GISE-LABEL: atomic_swap_1d:
; GFX12-GISE:       ; %bb.0:
; GFX12-GISE-NEXT:    image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX12-GISE-NEXT:    s_endpgm
;
; GFX12-LABEL: atomic_swap_1d:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX12-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.image.atomic.swap.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @atomic_swap_1d_i64(<8 x i32> inreg %rsrc, i64 %data, i32 %s) {
; GFX10PLUS-GISE-LABEL: atomic_swap_1d_i64:
; GFX10PLUS-GISE:       ; %bb.0:
; GFX10PLUS-GISE-NEXT:    image_atomic_swap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-GISE-NEXT:    s_endpgm
;
; GFX10PLUS-LABEL: atomic_swap_1d_i64:
; GFX10PLUS:       ; %bb.0:
; GFX10PLUS-NEXT:    image_atomic_swap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-NEXT:    s_endpgm
;
; GFX12-GISE-LABEL: atomic_swap_1d_i64:
; GFX12-GISE:       ; %bb.0:
; GFX12-GISE-NEXT:    image_atomic_swap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D
; GFX12-GISE-NEXT:    s_endpgm
;
; GFX12-LABEL: atomic_swap_1d_i64:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    image_atomic_swap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D
; GFX12-NEXT:    s_endpgm
  %v = call i64 @llvm.amdgcn.image.atomic.swap.1d.i64.i32(i64 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @atomic_swap_1d_float(<8 x i32> inreg %rsrc, float %data, i32 %s) {
; GFX10PLUS-GISE-LABEL: atomic_swap_1d_float:
; GFX10PLUS-GISE:       ; %bb.0:
; GFX10PLUS-GISE-NEXT:    image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-GISE-NEXT:    s_endpgm
;
; GFX10PLUS-LABEL: atomic_swap_1d_float:
; GFX10PLUS:       ; %bb.0:
; GFX10PLUS-NEXT:    image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-NEXT:    s_endpgm
;
; GFX12-GISE-LABEL: atomic_swap_1d_float:
; GFX12-GISE:       ; %bb.0:
; GFX12-GISE-NEXT:    image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX12-GISE-NEXT:    s_endpgm
;
; GFX12-LABEL: atomic_swap_1d_float:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX12-NEXT:    s_endpgm
  %v = call float @llvm.amdgcn.image.atomic.swap.1d.f32.i32(float %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @atomic_add_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
; GFX10PLUS-GISE-LABEL: atomic_add_1d:
; GFX10PLUS-GISE:       ; %bb.0:
; GFX10PLUS-GISE-NEXT:    image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-GISE-NEXT:    s_endpgm
;
; GFX10PLUS-LABEL: atomic_add_1d:
; GFX10PLUS:       ; %bb.0:
; GFX10PLUS-NEXT:    image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-NEXT:    s_endpgm
;
; GFX12-GISE-LABEL: atomic_add_1d:
; GFX12-GISE:       ; %bb.0:
; GFX12-GISE-NEXT:    image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX12-GISE-NEXT:    s_endpgm
;
; GFX12-LABEL: atomic_add_1d:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX12-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.image.atomic.add.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @atomic_sub_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
; GFX10PLUS-GISE-LABEL: atomic_sub_1d:
; GFX10PLUS-GISE:       ; %bb.0:
; GFX10PLUS-GISE-NEXT:    image_atomic_sub v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-GISE-NEXT:    s_endpgm
;
; GFX10PLUS-LABEL: atomic_sub_1d:
; GFX10PLUS:       ; %bb.0:
; GFX10PLUS-NEXT:    image_atomic_sub v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-NEXT:    s_endpgm
;
; GFX12-GISE-LABEL: atomic_sub_1d:
; GFX12-GISE:       ; %bb.0:
; GFX12-GISE-NEXT:    image_atomic_sub_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX12-GISE-NEXT:    s_endpgm
;
; GFX12-LABEL: atomic_sub_1d:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    image_atomic_sub_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX12-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.image.atomic.sub.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @atomic_smin_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
; GFX10PLUS-GISE-LABEL: atomic_smin_1d:
; GFX10PLUS-GISE:       ; %bb.0:
; GFX10PLUS-GISE-NEXT:    image_atomic_smin v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-GISE-NEXT:    s_endpgm
;
; GFX10PLUS-LABEL: atomic_smin_1d:
; GFX10PLUS:       ; %bb.0:
; GFX10PLUS-NEXT:    image_atomic_smin v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-NEXT:    s_endpgm
;
; GFX12-GISE-LABEL: atomic_smin_1d:
; GFX12-GISE:       ; %bb.0:
; GFX12-GISE-NEXT:    image_atomic_min_int v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX12-GISE-NEXT:    s_endpgm
;
; GFX12-LABEL: atomic_smin_1d:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    image_atomic_min_int v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX12-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.image.atomic.smin.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @atomic_umin_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
; GFX10PLUS-GISE-LABEL: atomic_umin_1d:
; GFX10PLUS-GISE:       ; %bb.0:
; GFX10PLUS-GISE-NEXT:    image_atomic_umin v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-GISE-NEXT:    s_endpgm
;
; GFX10PLUS-LABEL: atomic_umin_1d:
; GFX10PLUS:       ; %bb.0:
; GFX10PLUS-NEXT:    image_atomic_umin v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-NEXT:    s_endpgm
;
; GFX12-GISE-LABEL: atomic_umin_1d:
; GFX12-GISE:       ; %bb.0:
; GFX12-GISE-NEXT:    image_atomic_min_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX12-GISE-NEXT:    s_endpgm
;
; GFX12-LABEL: atomic_umin_1d:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    image_atomic_min_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX12-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.image.atomic.umin.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @atomic_smax_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
; GFX10PLUS-GISE-LABEL: atomic_smax_1d:
; GFX10PLUS-GISE:       ; %bb.0:
; GFX10PLUS-GISE-NEXT:    image_atomic_smax v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-GISE-NEXT:    s_endpgm
;
; GFX10PLUS-LABEL: atomic_smax_1d:
; GFX10PLUS:       ; %bb.0:
; GFX10PLUS-NEXT:    image_atomic_smax v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-NEXT:    s_endpgm
;
; GFX12-GISE-LABEL: atomic_smax_1d:
; GFX12-GISE:       ; %bb.0:
; GFX12-GISE-NEXT:    image_atomic_max_int v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX12-GISE-NEXT:    s_endpgm
;
; GFX12-LABEL: atomic_smax_1d:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    image_atomic_max_int v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX12-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.image.atomic.smax.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @atomic_umax_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
; GFX10PLUS-GISE-LABEL: atomic_umax_1d:
; GFX10PLUS-GISE:       ; %bb.0:
; GFX10PLUS-GISE-NEXT:    image_atomic_umax v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-GISE-NEXT:    s_endpgm
;
; GFX10PLUS-LABEL: atomic_umax_1d:
; GFX10PLUS:       ; %bb.0:
; GFX10PLUS-NEXT:    image_atomic_umax v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-NEXT:    s_endpgm
;
; GFX12-GISE-LABEL: atomic_umax_1d:
; GFX12-GISE:       ; %bb.0:
; GFX12-GISE-NEXT:    image_atomic_max_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX12-GISE-NEXT:    s_endpgm
;
; GFX12-LABEL: atomic_umax_1d:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    image_atomic_max_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX12-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.image.atomic.umax.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @atomic_and_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
; GFX10PLUS-GISE-LABEL: atomic_and_1d:
; GFX10PLUS-GISE:       ; %bb.0:
; GFX10PLUS-GISE-NEXT:    image_atomic_and v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-GISE-NEXT:    s_endpgm
;
; GFX10PLUS-LABEL: atomic_and_1d:
; GFX10PLUS:       ; %bb.0:
; GFX10PLUS-NEXT:    image_atomic_and v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-NEXT:    s_endpgm
;
; GFX12-GISE-LABEL: atomic_and_1d:
; GFX12-GISE:       ; %bb.0:
; GFX12-GISE-NEXT:    image_atomic_and v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX12-GISE-NEXT:    s_endpgm
;
; GFX12-LABEL: atomic_and_1d:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    image_atomic_and v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX12-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.image.atomic.and.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @atomic_or_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
; GFX10PLUS-GISE-LABEL: atomic_or_1d:
; GFX10PLUS-GISE:       ; %bb.0:
; GFX10PLUS-GISE-NEXT:    image_atomic_or v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-GISE-NEXT:    s_endpgm
;
; GFX10PLUS-LABEL: atomic_or_1d:
; GFX10PLUS:       ; %bb.0:
; GFX10PLUS-NEXT:    image_atomic_or v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-NEXT:    s_endpgm
;
; GFX12-GISE-LABEL: atomic_or_1d:
; GFX12-GISE:       ; %bb.0:
; GFX12-GISE-NEXT:    image_atomic_or v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX12-GISE-NEXT:    s_endpgm
;
; GFX12-LABEL: atomic_or_1d:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    image_atomic_or v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX12-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.image.atomic.or.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @atomic_xor_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
; GFX10PLUS-GISE-LABEL: atomic_xor_1d:
; GFX10PLUS-GISE:       ; %bb.0:
; GFX10PLUS-GISE-NEXT:    image_atomic_xor v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-GISE-NEXT:    s_endpgm
;
; GFX10PLUS-LABEL: atomic_xor_1d:
; GFX10PLUS:       ; %bb.0:
; GFX10PLUS-NEXT:    image_atomic_xor v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-NEXT:    s_endpgm
;
; GFX12-GISE-LABEL: atomic_xor_1d:
; GFX12-GISE:       ; %bb.0:
; GFX12-GISE-NEXT:    image_atomic_xor v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX12-GISE-NEXT:    s_endpgm
;
; GFX12-LABEL: atomic_xor_1d:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    image_atomic_xor v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX12-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.image.atomic.xor.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @atomic_inc_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
; GFX10PLUS-GISE-LABEL: atomic_inc_1d:
; GFX10PLUS-GISE:       ; %bb.0:
; GFX10PLUS-GISE-NEXT:    image_atomic_inc v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-GISE-NEXT:    s_endpgm
;
; GFX10PLUS-LABEL: atomic_inc_1d:
; GFX10PLUS:       ; %bb.0:
; GFX10PLUS-NEXT:    image_atomic_inc v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-NEXT:    s_endpgm
;
; GFX12-GISE-LABEL: atomic_inc_1d:
; GFX12-GISE:       ; %bb.0:
; GFX12-GISE-NEXT:    image_atomic_inc_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX12-GISE-NEXT:    s_endpgm
;
; GFX12-LABEL: atomic_inc_1d:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    image_atomic_inc_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX12-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.image.atomic.inc.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @atomic_dec_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
; GFX10PLUS-GISE-LABEL: atomic_dec_1d:
; GFX10PLUS-GISE:       ; %bb.0:
; GFX10PLUS-GISE-NEXT:    image_atomic_dec v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-GISE-NEXT:    s_endpgm
;
; GFX10PLUS-LABEL: atomic_dec_1d:
; GFX10PLUS:       ; %bb.0:
; GFX10PLUS-NEXT:    image_atomic_dec v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-NEXT:    s_endpgm
;
; GFX12-GISE-LABEL: atomic_dec_1d:
; GFX12-GISE:       ; %bb.0:
; GFX12-GISE-NEXT:    image_atomic_dec_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX12-GISE-NEXT:    s_endpgm
;
; GFX12-LABEL: atomic_dec_1d:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    image_atomic_dec_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D
; GFX12-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.image.atomic.dec.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @atomic_cmpswap_1d(<8 x i32> inreg %rsrc, i32 %cmp, i32 %swap, i32 %s) {
; GFX10PLUS-GISE-LABEL: atomic_cmpswap_1d:
; GFX10PLUS-GISE:       ; %bb.0:
; GFX10PLUS-GISE-NEXT:    image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-GISE-NEXT:    s_endpgm
;
; GFX10PLUS-LABEL: atomic_cmpswap_1d:
; GFX10PLUS:       ; %bb.0:
; GFX10PLUS-NEXT:    image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-NEXT:    s_endpgm
;
; GFX12-GISE-LABEL: atomic_cmpswap_1d:
; GFX12-GISE:       ; %bb.0:
; GFX12-GISE-NEXT:    image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D
; GFX12-GISE-NEXT:    s_endpgm
;
; GFX12-LABEL: atomic_cmpswap_1d:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D
; GFX12-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.image.atomic.cmpswap.1d.i32.i32(i32 %cmp, i32 %swap, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @atomic_cmpswap_1d_64(<8 x i32> inreg %rsrc, i64 %cmp, i64 %swap, i32 %s) {
; GFX10PLUS-GISE-LABEL: atomic_cmpswap_1d_64:
; GFX10PLUS-GISE:       ; %bb.0:
; GFX10PLUS-GISE-NEXT:    image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-GISE-NEXT:    s_endpgm
;
; GFX10PLUS-LABEL: atomic_cmpswap_1d_64:
; GFX10PLUS:       ; %bb.0:
; GFX10PLUS-NEXT:    image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm
; GFX10PLUS-NEXT:    s_endpgm
;
; GFX12-GISE-LABEL: atomic_cmpswap_1d_64:
; GFX12-GISE:       ; %bb.0:
; GFX12-GISE-NEXT:    image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX12-GISE-NEXT:    s_endpgm
;
; GFX12-LABEL: atomic_cmpswap_1d_64:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D
; GFX12-NEXT:    s_endpgm
  %v = call i64 @llvm.amdgcn.image.atomic.cmpswap.1d.i64.i32(i64 %cmp, i64 %swap, i32 %s, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @atomic_add_2d(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t) {
; GFX10PLUS-GISE-LABEL: atomic_add_2d:
; GFX10PLUS-GISE:       ; %bb.0:
; GFX10PLUS-GISE-NEXT:    image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm
; GFX10PLUS-GISE-NEXT:    s_endpgm
;
; GFX10PLUS-LABEL: atomic_add_2d:
; GFX10PLUS:       ; %bb.0:
; GFX10PLUS-NEXT:    image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm
; GFX10PLUS-NEXT:    s_endpgm
;
; GFX12-GISE-LABEL: atomic_add_2d:
; GFX12-GISE:       ; %bb.0:
; GFX12-GISE-NEXT:    image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
; GFX12-GISE-NEXT:    s_endpgm
;
; GFX12-LABEL: atomic_add_2d:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D
; GFX12-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.image.atomic.add.2d.i32.i32(i32 %data, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @atomic_add_3d(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t, i32 %r) {
; GFX10PLUS-GISE-LABEL: atomic_add_3d:
; GFX10PLUS-GISE:       ; %bb.0:
; GFX10PLUS-GISE-NEXT:    image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D unorm
; GFX10PLUS-GISE-NEXT:    s_endpgm
;
; GFX10PLUS-LABEL: atomic_add_3d:
; GFX10PLUS:       ; %bb.0:
; GFX10PLUS-NEXT:    image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D unorm
; GFX10PLUS-NEXT:    s_endpgm
;
; GFX12-GISE-LABEL: atomic_add_3d:
; GFX12-GISE:       ; %bb.0:
; GFX12-GISE-NEXT:    image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D
; GFX12-GISE-NEXT:    s_endpgm
;
; GFX12-LABEL: atomic_add_3d:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D
; GFX12-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.image.atomic.add.3d.i32.i32(i32 %data, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @atomic_add_cube(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t, i32 %face) {
; GFX10PLUS-GISE-LABEL: atomic_add_cube:
; GFX10PLUS-GISE:       ; %bb.0:
; GFX10PLUS-GISE-NEXT:    image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_CUBE unorm
; GFX10PLUS-GISE-NEXT:    s_endpgm
;
; GFX10PLUS-LABEL: atomic_add_cube:
; GFX10PLUS:       ; %bb.0:
; GFX10PLUS-NEXT:    image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_CUBE unorm
; GFX10PLUS-NEXT:    s_endpgm
;
; GFX12-GISE-LABEL: atomic_add_cube:
; GFX12-GISE:       ; %bb.0:
; GFX12-GISE-NEXT:    image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_CUBE
; GFX12-GISE-NEXT:    s_endpgm
;
; GFX12-LABEL: atomic_add_cube:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_CUBE
; GFX12-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.image.atomic.add.cube.i32.i32(i32 %data, i32 %s, i32 %t, i32 %face, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @atomic_add_1darray(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %slice) {
; GFX10PLUS-GISE-LABEL: atomic_add_1darray:
; GFX10PLUS-GISE:       ; %bb.0:
; GFX10PLUS-GISE-NEXT:    image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY unorm
; GFX10PLUS-GISE-NEXT:    s_endpgm
;
; GFX10PLUS-LABEL: atomic_add_1darray:
; GFX10PLUS:       ; %bb.0:
; GFX10PLUS-NEXT:    image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY unorm
; GFX10PLUS-NEXT:    s_endpgm
;
; GFX12-GISE-LABEL: atomic_add_1darray:
; GFX12-GISE:       ; %bb.0:
; GFX12-GISE-NEXT:    image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY
; GFX12-GISE-NEXT:    s_endpgm
;
; GFX12-LABEL: atomic_add_1darray:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY
; GFX12-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.image.atomic.add.1darray.i32.i32(i32 %data, i32 %s, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @atomic_add_2darray(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t, i32 %slice) {
; GFX10PLUS-GISE-LABEL: atomic_add_2darray:
; GFX10PLUS-GISE:       ; %bb.0:
; GFX10PLUS-GISE-NEXT:    image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY unorm
; GFX10PLUS-GISE-NEXT:    s_endpgm
;
; GFX10PLUS-LABEL: atomic_add_2darray:
; GFX10PLUS:       ; %bb.0:
; GFX10PLUS-NEXT:    image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY unorm
; GFX10PLUS-NEXT:    s_endpgm
;
; GFX12-GISE-LABEL: atomic_add_2darray:
; GFX12-GISE:       ; %bb.0:
; GFX12-GISE-NEXT:    image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY
; GFX12-GISE-NEXT:    s_endpgm
;
; GFX12-LABEL: atomic_add_2darray:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY
; GFX12-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.image.atomic.add.2darray.i32.i32(i32 %data, i32 %s, i32 %t, i32 %slice, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @atomic_add_2dmsaa(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t, i32 %fragid) {
; GFX10PLUS-GISE-LABEL: atomic_add_2dmsaa:
; GFX10PLUS-GISE:       ; %bb.0:
; GFX10PLUS-GISE-NEXT:    image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm
; GFX10PLUS-GISE-NEXT:    s_endpgm
;
; GFX10PLUS-LABEL: atomic_add_2dmsaa:
; GFX10PLUS:       ; %bb.0:
; GFX10PLUS-NEXT:    image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm
; GFX10PLUS-NEXT:    s_endpgm
;
; GFX12-GISE-LABEL: atomic_add_2dmsaa:
; GFX12-GISE:       ; %bb.0:
; GFX12-GISE-NEXT:    image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA
; GFX12-GISE-NEXT:    s_endpgm
;
; GFX12-LABEL: atomic_add_2dmsaa:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA
; GFX12-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.image.atomic.add.2dmsaa.i32.i32(i32 %data, i32 %s, i32 %t, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @atomic_add_2darraymsaa(<8 x i32> inreg %rsrc, i32 %data, i32 %s, i32 %t, i32 %slice, i32 %fragid) {
; GFX10PLUS-GISE-LABEL: atomic_add_2darraymsaa:
; GFX10PLUS-GISE:       ; %bb.0:
; GFX10PLUS-GISE-NEXT:    image_atomic_add v0, v[1:4], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm
; GFX10PLUS-GISE-NEXT:    s_endpgm
;
; GFX10PLUS-LABEL: atomic_add_2darraymsaa:
; GFX10PLUS:       ; %bb.0:
; GFX10PLUS-NEXT:    image_atomic_add v0, v[1:4], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm
; GFX10PLUS-NEXT:    s_endpgm
;
; GFX12-GISE-LABEL: atomic_add_2darraymsaa:
; GFX12-GISE:       ; %bb.0:
; GFX12-GISE-NEXT:    image_atomic_add_uint v0, [v1, v2, v3, v4], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
; GFX12-GISE-NEXT:    s_endpgm
;
; GFX12-LABEL: atomic_add_2darraymsaa:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    image_atomic_add_uint v0, [v1, v2, v3, v4], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY
; GFX12-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.image.atomic.add.2darraymsaa.i32.i32(i32 %data, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0)
  ret void
}

define amdgpu_ps void @atomic_add_1d_slc(<8 x i32> inreg %rsrc, i32 %data, i32 %s) {
; GFX10PLUS-GISE-LABEL: atomic_add_1d_slc:
; GFX10PLUS-GISE:       ; %bb.0:
; GFX10PLUS-GISE-NEXT:    image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm slc
; GFX10PLUS-GISE-NEXT:    s_endpgm
;
; GFX10PLUS-LABEL: atomic_add_1d_slc:
; GFX10PLUS:       ; %bb.0:
; GFX10PLUS-NEXT:    image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm slc
; GFX10PLUS-NEXT:    s_endpgm
;
; GFX12-GISE-LABEL: atomic_add_1d_slc:
; GFX12-GISE:       ; %bb.0:
; GFX12-GISE-NEXT:    image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT
; GFX12-GISE-NEXT:    s_endpgm
;
; GFX12-LABEL: atomic_add_1d_slc:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT
; GFX12-NEXT:    s_endpgm
  %v = call i32 @llvm.amdgcn.image.atomic.add.1d.i32.i32(i32 %data, i32 %s, <8 x i32> %rsrc, i32 0, i32 2)
  ret void
}