; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s

define void @main(i1 %arg) #0 {
; CHECK-LABEL: main:
; CHECK:       ; %bb.0: ; %bb
; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT:    s_xor_saveexec_b64 s[4:5], -1
; CHECK-NEXT:    buffer_store_dword v5, off, s[0:3], s32 ; 4-byte Folded Spill
; CHECK-NEXT:    buffer_store_dword v6, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; CHECK-NEXT:    s_mov_b64 exec, s[4:5]
; CHECK-NEXT:    v_writelane_b32 v5, s30, 0
; CHECK-NEXT:    v_writelane_b32 v5, s31, 1
; CHECK-NEXT:    v_writelane_b32 v5, s36, 2
; CHECK-NEXT:    v_writelane_b32 v5, s37, 3
; CHECK-NEXT:    v_writelane_b32 v5, s38, 4
; CHECK-NEXT:    v_writelane_b32 v5, s39, 5
; CHECK-NEXT:    v_writelane_b32 v5, s48, 6
; CHECK-NEXT:    v_writelane_b32 v5, s49, 7
; CHECK-NEXT:    v_writelane_b32 v5, s50, 8
; CHECK-NEXT:    v_writelane_b32 v5, s51, 9
; CHECK-NEXT:    v_writelane_b32 v5, s52, 10
; CHECK-NEXT:    v_writelane_b32 v5, s53, 11
; CHECK-NEXT:    v_writelane_b32 v5, s54, 12
; CHECK-NEXT:    v_writelane_b32 v5, s55, 13
; CHECK-NEXT:    s_getpc_b64 s[24:25]
; CHECK-NEXT:    v_writelane_b32 v5, s64, 14
; CHECK-NEXT:    s_movk_i32 s4, 0xf0
; CHECK-NEXT:    s_mov_b32 s5, s24
; CHECK-NEXT:    v_writelane_b32 v5, s65, 15
; CHECK-NEXT:    s_load_dwordx16 s[8:23], s[4:5], 0x0
; CHECK-NEXT:    s_mov_b64 s[4:5], 0
; CHECK-NEXT:    v_writelane_b32 v5, s66, 16
; CHECK-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0
; CHECK-NEXT:    v_writelane_b32 v5, s67, 17
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    s_movk_i32 s6, 0x130
; CHECK-NEXT:    s_mov_b32 s7, s24
; CHECK-NEXT:    v_writelane_b32 v5, s68, 18
; CHECK-NEXT:    s_load_dwordx16 s[36:51], s[6:7], 0x0
; CHECK-NEXT:    v_writelane_b32 v5, s69, 19
; CHECK-NEXT:    v_writelane_b32 v5, s70, 20
; CHECK-NEXT:    s_mov_b32 s68, 0
; CHECK-NEXT:    v_mov_b32_e32 v1, 0
; CHECK-NEXT:    v_writelane_b32 v5, s71, 21
; CHECK-NEXT:    v_mov_b32_e32 v2, s4
; CHECK-NEXT:    v_mov_b32_e32 v3, v1
; CHECK-NEXT:    s_mov_b32 s69, s68
; CHECK-NEXT:    s_mov_b32 s70, s68
; CHECK-NEXT:    s_mov_b32 s71, s68
; CHECK-NEXT:    image_sample_lz v3, v[2:3], s[16:23], s[68:71] dmask:0x1
; CHECK-NEXT:    v_mov_b32_e32 v2, v1
; CHECK-NEXT:    ; implicit-def: $vgpr6 : SGPR spill to VGPR lane
; CHECK-NEXT:    s_mov_b32 s6, 48
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    v_writelane_b32 v6, s36, 0
; CHECK-NEXT:    v_writelane_b32 v6, s37, 1
; CHECK-NEXT:    v_writelane_b32 v6, s38, 2
; CHECK-NEXT:    v_writelane_b32 v6, s39, 3
; CHECK-NEXT:    v_writelane_b32 v6, s40, 4
; CHECK-NEXT:    v_writelane_b32 v6, s41, 5
; CHECK-NEXT:    image_sample_lz v4, v[1:2], s[36:43], s[68:71] dmask:0x1
; CHECK-NEXT:    v_writelane_b32 v6, s42, 6
; CHECK-NEXT:    v_writelane_b32 v6, s43, 7
; CHECK-NEXT:    v_writelane_b32 v6, s44, 8
; CHECK-NEXT:    v_writelane_b32 v6, s45, 9
; CHECK-NEXT:    v_writelane_b32 v6, s46, 10
; CHECK-NEXT:    v_writelane_b32 v6, s47, 11
; CHECK-NEXT:    v_writelane_b32 v6, s48, 12
; CHECK-NEXT:    v_writelane_b32 v6, s49, 13
; CHECK-NEXT:    v_writelane_b32 v6, s50, 14
; CHECK-NEXT:    s_movk_i32 s56, 0x1f0
; CHECK-NEXT:    s_movk_i32 s72, 0x2f0
; CHECK-NEXT:    s_mov_b32 s57, s24
; CHECK-NEXT:    s_mov_b32 s73, s24
; CHECK-NEXT:    v_writelane_b32 v6, s51, 15
; CHECK-NEXT:    s_load_dwordx8 s[24:31], s[6:7], 0x0
; CHECK-NEXT:    s_load_dwordx16 s[36:51], s[56:57], 0x0
; CHECK-NEXT:    v_and_b32_e32 v0, 1, v0
; CHECK-NEXT:    s_load_dwordx16 s[52:67], s[72:73], 0x0
; CHECK-NEXT:    v_cmp_ne_u32_e64 s[4:5], 1, v0
; CHECK-NEXT:    s_waitcnt vmcnt(0)
; CHECK-NEXT:    v_mul_f32_e32 v0, v4, v3
; CHECK-NEXT:    s_and_saveexec_b64 s[6:7], s[4:5]
; CHECK-NEXT:    s_xor_b64 s[6:7], exec, s[6:7]
; CHECK-NEXT:    s_cbranch_execz .LBB0_3
; CHECK-NEXT:  ; %bb.1: ; %bb48
; CHECK-NEXT:    image_sample_lz v3, v[1:2], s[16:23], s[68:71] dmask:0x1
; CHECK-NEXT:    v_mov_b32_e32 v2, 0
; CHECK-NEXT:    s_and_b64 vcc, exec, -1
; CHECK-NEXT:  .LBB0_2: ; %bb50
; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT:    s_mov_b32 s69, s68
; CHECK-NEXT:    s_mov_b32 s70, s68
; CHECK-NEXT:    s_mov_b32 s71, s68
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    image_sample_lz v4, v[1:2], s[44:51], s[28:31] dmask:0x1
; CHECK-NEXT:    s_nop 0
; CHECK-NEXT:    image_sample_lz v1, v[1:2], s[60:67], s[68:71] dmask:0x1
; CHECK-NEXT:    s_waitcnt vmcnt(0)
; CHECK-NEXT:    v_sub_f32_e32 v1, v1, v4
; CHECK-NEXT:    v_mul_f32_e32 v1, v1, v0
; CHECK-NEXT:    v_mul_f32_e32 v1, v1, v3
; CHECK-NEXT:    s_mov_b64 vcc, vcc
; CHECK-NEXT:    s_cbranch_vccnz .LBB0_2
; CHECK-NEXT:  .LBB0_3: ; %Flow14
; CHECK-NEXT:    s_andn2_saveexec_b64 s[6:7], s[6:7]
; CHECK-NEXT:    s_cbranch_execz .LBB0_10
; CHECK-NEXT:  ; %bb.4: ; %bb32
; CHECK-NEXT:    s_and_saveexec_b64 s[16:17], s[4:5]
; CHECK-NEXT:    s_xor_b64 s[4:5], exec, s[16:17]
; CHECK-NEXT:    s_cbranch_execz .LBB0_6
; CHECK-NEXT:  ; %bb.5: ; %bb43
; CHECK-NEXT:    s_mov_b32 s16, 0
; CHECK-NEXT:    s_mov_b32 s17, s16
; CHECK-NEXT:    v_mov_b32_e32 v2, s16
; CHECK-NEXT:    v_mov_b32_e32 v3, s17
; CHECK-NEXT:    s_mov_b32 s18, s16
; CHECK-NEXT:    s_mov_b32 s19, s16
; CHECK-NEXT:    image_sample_lz v1, v[2:3], s[8:15], s[16:19] dmask:0x1
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    s_mov_b64 s[8:9], s[36:37]
; CHECK-NEXT:    s_mov_b64 s[10:11], s[38:39]
; CHECK-NEXT:    s_mov_b64 s[12:13], s[40:41]
; CHECK-NEXT:    s_mov_b64 s[14:15], s[42:43]
; CHECK-NEXT:    v_readlane_b32 s36, v6, 0
; CHECK-NEXT:    v_readlane_b32 s44, v6, 8
; CHECK-NEXT:    v_readlane_b32 s45, v6, 9
; CHECK-NEXT:    v_readlane_b32 s46, v6, 10
; CHECK-NEXT:    v_readlane_b32 s47, v6, 11
; CHECK-NEXT:    v_readlane_b32 s48, v6, 12
; CHECK-NEXT:    v_readlane_b32 s49, v6, 13
; CHECK-NEXT:    v_readlane_b32 s50, v6, 14
; CHECK-NEXT:    v_readlane_b32 s51, v6, 15
; CHECK-NEXT:    v_readlane_b32 s37, v6, 1
; CHECK-NEXT:    v_readlane_b32 s38, v6, 2
; CHECK-NEXT:    v_readlane_b32 s39, v6, 3
; CHECK-NEXT:    v_readlane_b32 s40, v6, 4
; CHECK-NEXT:    v_readlane_b32 s41, v6, 5
; CHECK-NEXT:    image_sample_lz v0, v[2:3], s[44:51], s[24:27] dmask:0x1
; CHECK-NEXT:    v_readlane_b32 s42, v6, 6
; CHECK-NEXT:    v_readlane_b32 s43, v6, 7
; CHECK-NEXT:    v_mov_b32_e32 v2, 0
; CHECK-NEXT:    s_mov_b64 s[42:43], s[14:15]
; CHECK-NEXT:    v_mov_b32_e32 v3, v2
; CHECK-NEXT:    s_mov_b64 s[40:41], s[12:13]
; CHECK-NEXT:    s_mov_b64 s[38:39], s[10:11]
; CHECK-NEXT:    s_mov_b64 s[36:37], s[8:9]
; CHECK-NEXT:    s_waitcnt vmcnt(1)
; CHECK-NEXT:    buffer_store_dwordx3 v[1:3], off, s[16:19], 0
; CHECK-NEXT:    s_waitcnt vmcnt(1)
; CHECK-NEXT:    buffer_store_dwordx4 v[0:3], off, s[16:19], 0
; CHECK-NEXT:    ; implicit-def: $vgpr0
; CHECK-NEXT:  .LBB0_6: ; %Flow12
; CHECK-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]
; CHECK-NEXT:    s_cbranch_execz .LBB0_9
; CHECK-NEXT:  ; %bb.7: ; %bb33.preheader
; CHECK-NEXT:    s_mov_b32 s8, 0
; CHECK-NEXT:    s_mov_b32 s12, s8
; CHECK-NEXT:    s_mov_b32 s13, s8
; CHECK-NEXT:    v_mov_b32_e32 v1, s12
; CHECK-NEXT:    s_mov_b32 s9, s8
; CHECK-NEXT:    s_mov_b32 s10, s8
; CHECK-NEXT:    s_mov_b32 s11, s8
; CHECK-NEXT:    v_mov_b32_e32 v2, s13
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    image_sample_lz v3, v[1:2], s[36:43], s[8:11] dmask:0x1
; CHECK-NEXT:    image_sample_lz v4, v[1:2], s[52:59], s[8:11] dmask:0x1
; CHECK-NEXT:    s_and_b64 vcc, exec, 0
; CHECK-NEXT:    s_waitcnt vmcnt(0)
; CHECK-NEXT:    v_sub_f32_e32 v1, v4, v3
; CHECK-NEXT:    v_mul_f32_e32 v0, v1, v0
; CHECK-NEXT:    v_mov_b32_e32 v1, 0
; CHECK-NEXT:  .LBB0_8: ; %bb33
; CHECK-NEXT:    ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT:    v_add_f32_e32 v2, v1, v0
; CHECK-NEXT:    v_sub_f32_e32 v1, v1, v2
; CHECK-NEXT:    s_mov_b64 vcc, vcc
; CHECK-NEXT:    s_cbranch_vccz .LBB0_8
; CHECK-NEXT:  .LBB0_9: ; %Flow13
; CHECK-NEXT:    s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT:  .LBB0_10: ; %UnifiedReturnBlock
; CHECK-NEXT:    s_or_b64 exec, exec, s[6:7]
; CHECK-NEXT:    v_readlane_b32 s71, v5, 21
; CHECK-NEXT:    v_readlane_b32 s70, v5, 20
; CHECK-NEXT:    v_readlane_b32 s69, v5, 19
; CHECK-NEXT:    v_readlane_b32 s68, v5, 18
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    v_readlane_b32 s67, v5, 17
; CHECK-NEXT:    v_readlane_b32 s66, v5, 16
; CHECK-NEXT:    v_readlane_b32 s65, v5, 15
; CHECK-NEXT:    v_readlane_b32 s64, v5, 14
; CHECK-NEXT:    v_readlane_b32 s55, v5, 13
; CHECK-NEXT:    v_readlane_b32 s54, v5, 12
; CHECK-NEXT:    v_readlane_b32 s53, v5, 11
; CHECK-NEXT:    v_readlane_b32 s52, v5, 10
; CHECK-NEXT:    v_readlane_b32 s51, v5, 9
; CHECK-NEXT:    v_readlane_b32 s50, v5, 8
; CHECK-NEXT:    v_readlane_b32 s49, v5, 7
; CHECK-NEXT:    v_readlane_b32 s48, v5, 6
; CHECK-NEXT:    v_readlane_b32 s39, v5, 5
; CHECK-NEXT:    v_readlane_b32 s38, v5, 4
; CHECK-NEXT:    v_readlane_b32 s37, v5, 3
; CHECK-NEXT:    v_readlane_b32 s36, v5, 2
; CHECK-NEXT:    v_readlane_b32 s31, v5, 1
; CHECK-NEXT:    v_readlane_b32 s30, v5, 0
; CHECK-NEXT:    s_xor_saveexec_b64 s[4:5], -1
; CHECK-NEXT:    buffer_load_dword v5, off, s[0:3], s32 ; 4-byte Folded Reload
; CHECK-NEXT:    buffer_load_dword v6, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; CHECK-NEXT:    s_mov_b64 exec, s[4:5]
; CHECK-NEXT:    s_waitcnt vmcnt(0)
; CHECK-NEXT:    s_setpc_b64 s[30:31]
bb:
  %i = call i64 @llvm.amdgcn.s.getpc()
  %i1 = trunc i64 %i to i32
  %i2 = insertelement <2 x i32> zeroinitializer, i32 %i1, i64 1
  %i3 = bitcast <2 x i32> %i2 to i64
  %i4 = inttoptr i64 %i3 to ptr addrspace(4)
  %i5 = getelementptr i8, ptr addrspace(4) %i4, i64 48
  %i6 = load <4 x i32>, ptr addrspace(4) %i5, align 16
  %i7 = getelementptr i8, ptr addrspace(4) %i4, i64 64
  %i8 = load <4 x i32>, ptr addrspace(4) %i7, align 16
  %i9 = getelementptr i8, ptr addrspace(4) %i4, i64 240
  %i10 = load <8 x i32>, ptr addrspace(4) %i9, align 32
  %i11 = getelementptr i8, ptr addrspace(4) %i4, i64 272
  %i12 = load <8 x i32>, ptr addrspace(4) %i11, align 32
  %i13 = getelementptr i8, ptr addrspace(4) %i4, i64 304
  %i14 = load <8 x i32>, ptr addrspace(4) %i13, align 32
  %i15 = getelementptr i8, ptr addrspace(4) %i4, i64 336
  %i16 = load <8 x i32>, ptr addrspace(4) %i15, align 32
  %i17 = getelementptr i8, ptr addrspace(4) %i4, i64 496
  %i18 = load <8 x i32>, ptr addrspace(4) %i17, align 32
  %i19 = getelementptr i8, ptr addrspace(4) %i4, i64 528
  %i20 = load <8 x i32>, ptr addrspace(4) %i19, align 32
  %i21 = getelementptr i8, ptr addrspace(4) %i4, i64 752
  %i22 = load <8 x i32>, ptr addrspace(4) %i21, align 32
  %i23 = getelementptr i8, ptr addrspace(4) %i4, i64 784
  %i24 = load <8 x i32>, ptr addrspace(4) %i23, align 32
  %i25 = load <4 x float>, ptr addrspace(4) null, align 16
  %i26 = extractelement <4 x float> %i25, i64 0
  %i27 = call float @llvm.amdgcn.image.sample.lz.2d.f32.f32(i32 1, float %i26, float 0.000000e+00, <8 x i32> %i12, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)
  %i28 = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32(i32 1, float 0.000000e+00, float 0.000000e+00, <8 x i32> %i14, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)
  %i29 = extractelement <4 x float> %i28, i64 0
  %i30 = fmul float %i29, %i27
  %i31 = call <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32(i32 1, float 0.000000e+00, float 0.000000e+00, <8 x i32> %i16, <4 x i32> %i6, i1 false, i32 0, i32 0)
  br i1 %arg, label %bb32, label %bb48

bb32:                                             ; preds = %bb
  br i1 %arg, label %bb33, label %bb43

bb33:                                             ; preds = %bb33, %bb32
  %i34 = phi float [ %i42, %bb33 ], [ 0.000000e+00, %bb32 ]
  %i35 = call <2 x float> @llvm.amdgcn.image.sample.lz.2d.v2f32.f32(i32 1, float 0.000000e+00, float 0.000000e+00, <8 x i32> %i18, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)
  %i36 = extractelement <2 x float> %i35, i64 0
  %i37 = call <2 x float> @llvm.amdgcn.image.sample.lz.2d.v2f32.f32(i32 1, float 0.000000e+00, float 0.000000e+00, <8 x i32> %i22, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)
  %i38 = extractelement <2 x float> %i37, i64 0
  %i39 = fsub float %i38, %i36
  %i40 = fmul float %i39, %i30
  %i41 = fadd float %i34, %i40
  %i42 = fsub float %i34, %i41
  br label %bb33

bb43:                                             ; preds = %bb32
  %i44 = call float @llvm.amdgcn.image.sample.lz.2d.f32.f32(i32 1, float 0.000000e+00, float 0.000000e+00, <8 x i32> %i10, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)
  %i45 = bitcast float %i44 to i32
  %i46 = insertelement <3 x i32> zeroinitializer, i32 %i45, i64 0
  call void @llvm.amdgcn.raw.buffer.store.v3i32(<3 x i32> %i46, <4 x i32> zeroinitializer, i32 0, i32 0, i32 0)
  %i47 = bitcast <4 x float> %i31 to <4 x i32>
  call void @llvm.amdgcn.raw.buffer.store.v4i32(<4 x i32> %i47, <4 x i32> zeroinitializer, i32 0, i32 0, i32 0)
  ret void

bb48:                                             ; preds = %bb
  %i49 = call float @llvm.amdgcn.image.sample.lz.2d.f32.f32(i32 1, float 0.000000e+00, float 0.000000e+00, <8 x i32> %i12, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)
  br label %bb50

bb50:                                             ; preds = %bb50, %bb48
  %i51 = phi float [ 0.000000e+00, %bb48 ], [ %i58, %bb50 ]
  %i52 = call <2 x float> @llvm.amdgcn.image.sample.lz.2d.v2f32.f32(i32 1, float %i51, float 0.000000e+00, <8 x i32> %i20, <4 x i32> %i8, i1 false, i32 0, i32 0)
  %i53 = extractelement <2 x float> %i52, i64 0
  %i54 = call <2 x float> @llvm.amdgcn.image.sample.lz.2d.v2f32.f32(i32 1, float %i51, float 0.000000e+00, <8 x i32> %i24, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)
  %i55 = extractelement <2 x float> %i54, i64 0
  %i56 = fsub float %i55, %i53
  %i57 = fmul float %i56, %i30
  %i58 = fmul float %i57, %i49
  br label %bb50
}

declare i64 @llvm.amdgcn.s.getpc() #1
declare <4 x float> @llvm.amdgcn.image.sample.lz.2d.v4f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #2
declare float @llvm.amdgcn.image.sample.lz.2d.f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #2
declare <2 x float> @llvm.amdgcn.image.sample.lz.2d.v2f32.f32(i32 immarg, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #2
declare void @llvm.amdgcn.raw.buffer.store.v3i32(<3 x i32>, <4 x i32>, i32, i32, i32 immarg) #3
declare void @llvm.amdgcn.raw.buffer.store.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32 immarg) #3

attributes #0 = { "amdgpu-waves-per-eu"="10,10" }
attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(read) }
attributes #3 = { nocallback nofree nosync nounwind willreturn memory(write) }