; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn -mcpu=tahiti -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn -mcpu=tonga -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=GCN %s

; This used to crash because during intermediate control flow lowering, there
; was a sequence
;       s_mov_b64 s[0:1], exec
;       s_and_b64 s[2:3], s[0:1], s[2:3] ; def & use of the same register pair
;       ...
;       s_mov_b64_term exec, s[2:3]
; that was not treated correctly.
;
define amdgpu_ps void @ham(float %arg, float %arg1) #0 {
; GCN-LABEL: ham:
; GCN:       ; %bb.0: ; %bb
; GCN-NEXT:    v_cmp_lt_f32_e32 vcc, 0, v0
; GCN-NEXT:    v_cmp_lt_f32_e64 s[0:1], 0, v1
; GCN-NEXT:    s_and_b64 s[0:1], vcc, s[0:1]
; GCN-NEXT:    s_and_saveexec_b64 s[2:3], s[0:1]
; GCN-NEXT:  ; %bb.1: ; %bb4
; GCN-NEXT:    v_mov_b32_e32 v0, 4
; GCN-NEXT:    s_mov_b32 m0, -1
; GCN-NEXT:    ds_write_b32 v0, v0
; GCN-NEXT:    ; divergent unreachable
; GCN-NEXT:  ; %bb.2: ; %UnifiedReturnBlock
; GCN-NEXT:    s_endpgm
bb:
  %tmp = fcmp ogt float %arg, 0.000000e+00
  %tmp2 = fcmp ogt float %arg1, 0.000000e+00
  %tmp3 = and i1 %tmp, %tmp2
  br i1 %tmp3, label %bb4, label %bb5

bb4:                                              ; preds = %bb
  store volatile i32 4, ptr addrspace(3) poison
  unreachable

bb5:                                              ; preds = %bb
  ret void
}

attributes #0 = { nounwind readonly "InitialPSInputAddr"="36983" }
attributes #1 = { nounwind readnone }