# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=aarch64 -verify-machineinstrs -run-pass=aarch64-expand-pseudo -run-pass=aarch64-ldst-opt -debug-only=aarch64-ldst-opt %s -o - | FileCheck %s
# REQUIRES: asserts
---
name: test_fold_repeating_constant_load
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0
    ; CHECK-LABEL: name: test_fold_repeating_constant_load
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: renamable $x0 = MOVZXi 49370, 0
    ; CHECK-NEXT: renamable $x0 = MOVKXi $x0, 320, 16
    ; CHECK-NEXT: renamable $x0 = ORRXrs $x0, $x0, 32
    ; CHECK-NEXT: RET undef $lr, implicit $x0
    renamable $x0 = MOVi64imm 90284035103834330
    RET_ReallyLR implicit $x0
...
---
name: test_fold_repeating_constant_load_neg
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0
    ; CHECK-LABEL: name: test_fold_repeating_constant_load_neg
    ; CHECK: liveins: $x0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: renamable $x0 = MOVZXi 320, 0
    ; CHECK-NEXT: renamable $x0 = MOVKXi $x0, 49370, 16
    ; CHECK-NEXT: renamable $x0 = ORRXrs $x0, $x0, 32
    ; CHECK-NEXT: RET undef $lr, implicit $x0
    renamable $x0 = MOVi64imm -4550323095879417536
    RET_ReallyLR implicit $x0