; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-none-elf -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc -mtriple=aarch64-none-elf -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI

define i32 @and_eq_eq(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_eq_eq:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, eq
; CHECK-SD-NEXT:    cset w0, eq
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_eq_eq:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, eq
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, eq
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp eq i32 %s0, %s1
  %c1 = icmp eq i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_eq_ne(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_eq_ne:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #4, eq
; CHECK-SD-NEXT:    cset w0, ne
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_eq_ne:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, eq
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ne
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp eq i32 %s0, %s1
  %c1 = icmp ne i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_eq_ult(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_eq_ult:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #2, eq
; CHECK-SD-NEXT:    cset w0, lo
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_eq_ult:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, eq
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, lo
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp eq i32 %s0, %s1
  %c1 = icmp ult i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_eq_ule(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_eq_ule:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #2, eq
; CHECK-SD-NEXT:    cset w0, ls
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_eq_ule:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, eq
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ls
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp eq i32 %s0, %s1
  %c1 = icmp ule i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_eq_ugt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_eq_ugt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, eq
; CHECK-SD-NEXT:    cset w0, hi
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_eq_ugt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, eq
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, hi
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp eq i32 %s0, %s1
  %c1 = icmp ugt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_eq_uge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_eq_uge:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, eq
; CHECK-SD-NEXT:    cset w0, hs
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_eq_uge:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, eq
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, hs
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp eq i32 %s0, %s1
  %c1 = icmp uge i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_eq_slt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_eq_slt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, eq
; CHECK-SD-NEXT:    cset w0, lt
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_eq_slt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, eq
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, lt
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp eq i32 %s0, %s1
  %c1 = icmp slt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_eq_sle(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_eq_sle:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, eq
; CHECK-SD-NEXT:    cset w0, le
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_eq_sle:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, eq
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, le
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp eq i32 %s0, %s1
  %c1 = icmp sle i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_eq_sgt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_eq_sgt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #4, eq
; CHECK-SD-NEXT:    cset w0, gt
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_eq_sgt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, eq
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, gt
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp eq i32 %s0, %s1
  %c1 = icmp sgt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_eq_sge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_eq_sge:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #8, eq
; CHECK-SD-NEXT:    cset w0, ge
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_eq_sge:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, eq
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ge
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp eq i32 %s0, %s1
  %c1 = icmp sge i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ne_eq(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ne_eq:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, ne
; CHECK-SD-NEXT:    cset w0, eq
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ne_eq:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ne
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, eq
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ne i32 %s0, %s1
  %c1 = icmp eq i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ne_ne(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ne_ne:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #4, ne
; CHECK-SD-NEXT:    cset w0, ne
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ne_ne:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ne
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ne
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ne i32 %s0, %s1
  %c1 = icmp ne i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ne_ult(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ne_ult:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #2, ne
; CHECK-SD-NEXT:    cset w0, lo
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ne_ult:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ne
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, lo
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ne i32 %s0, %s1
  %c1 = icmp ult i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ne_ule(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ne_ule:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #2, ne
; CHECK-SD-NEXT:    cset w0, ls
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ne_ule:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ne
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ls
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ne i32 %s0, %s1
  %c1 = icmp ule i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ne_ugt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ne_ugt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, ne
; CHECK-SD-NEXT:    cset w0, hi
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ne_ugt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ne
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, hi
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ne i32 %s0, %s1
  %c1 = icmp ugt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ne_uge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ne_uge:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, ne
; CHECK-SD-NEXT:    cset w0, hs
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ne_uge:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ne
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, hs
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ne i32 %s0, %s1
  %c1 = icmp uge i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ne_slt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ne_slt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, ne
; CHECK-SD-NEXT:    cset w0, lt
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ne_slt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ne
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, lt
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ne i32 %s0, %s1
  %c1 = icmp slt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ne_sle(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ne_sle:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, ne
; CHECK-SD-NEXT:    cset w0, le
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ne_sle:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ne
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, le
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ne i32 %s0, %s1
  %c1 = icmp sle i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ne_sgt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ne_sgt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #4, ne
; CHECK-SD-NEXT:    cset w0, gt
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ne_sgt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ne
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, gt
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ne i32 %s0, %s1
  %c1 = icmp sgt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ne_sge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ne_sge:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #8, ne
; CHECK-SD-NEXT:    cset w0, ge
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ne_sge:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ne
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ge
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ne i32 %s0, %s1
  %c1 = icmp sge i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ult_eq(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ult_eq:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, lo
; CHECK-SD-NEXT:    cset w0, eq
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ult_eq:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, lo
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, eq
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ult i32 %s0, %s1
  %c1 = icmp eq i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ult_ne(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ult_ne:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #4, lo
; CHECK-SD-NEXT:    cset w0, ne
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ult_ne:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, lo
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ne
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ult i32 %s0, %s1
  %c1 = icmp ne i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ult_ult(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ult_ult:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #2, lo
; CHECK-SD-NEXT:    cset w0, lo
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ult_ult:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, lo
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, lo
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ult i32 %s0, %s1
  %c1 = icmp ult i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ult_ule(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ult_ule:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #2, lo
; CHECK-SD-NEXT:    cset w0, ls
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ult_ule:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, lo
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ls
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ult i32 %s0, %s1
  %c1 = icmp ule i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ult_ugt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ult_ugt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, lo
; CHECK-SD-NEXT:    cset w0, hi
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ult_ugt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, lo
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, hi
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ult i32 %s0, %s1
  %c1 = icmp ugt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ult_uge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ult_uge:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, lo
; CHECK-SD-NEXT:    cset w0, hs
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ult_uge:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, lo
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, hs
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ult i32 %s0, %s1
  %c1 = icmp uge i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ult_slt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ult_slt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, lo
; CHECK-SD-NEXT:    cset w0, lt
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ult_slt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, lo
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, lt
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ult i32 %s0, %s1
  %c1 = icmp slt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ult_sle(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ult_sle:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, lo
; CHECK-SD-NEXT:    cset w0, le
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ult_sle:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, lo
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, le
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ult i32 %s0, %s1
  %c1 = icmp sle i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ult_sgt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ult_sgt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #4, lo
; CHECK-SD-NEXT:    cset w0, gt
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ult_sgt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, lo
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, gt
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ult i32 %s0, %s1
  %c1 = icmp sgt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ult_sge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ult_sge:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #8, lo
; CHECK-SD-NEXT:    cset w0, ge
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ult_sge:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, lo
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ge
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ult i32 %s0, %s1
  %c1 = icmp sge i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ule_eq(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ule_eq:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, ls
; CHECK-SD-NEXT:    cset w0, eq
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ule_eq:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ls
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, eq
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ule i32 %s0, %s1
  %c1 = icmp eq i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ule_ne(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ule_ne:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #4, ls
; CHECK-SD-NEXT:    cset w0, ne
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ule_ne:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ls
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ne
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ule i32 %s0, %s1
  %c1 = icmp ne i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ule_ult(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ule_ult:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #2, ls
; CHECK-SD-NEXT:    cset w0, lo
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ule_ult:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ls
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, lo
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ule i32 %s0, %s1
  %c1 = icmp ult i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ule_ule(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ule_ule:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #2, ls
; CHECK-SD-NEXT:    cset w0, ls
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ule_ule:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ls
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ls
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ule i32 %s0, %s1
  %c1 = icmp ule i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ule_ugt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ule_ugt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, ls
; CHECK-SD-NEXT:    cset w0, hi
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ule_ugt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ls
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, hi
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ule i32 %s0, %s1
  %c1 = icmp ugt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ule_uge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ule_uge:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, ls
; CHECK-SD-NEXT:    cset w0, hs
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ule_uge:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ls
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, hs
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ule i32 %s0, %s1
  %c1 = icmp uge i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ule_slt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ule_slt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, ls
; CHECK-SD-NEXT:    cset w0, lt
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ule_slt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ls
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, lt
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ule i32 %s0, %s1
  %c1 = icmp slt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ule_sle(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ule_sle:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, ls
; CHECK-SD-NEXT:    cset w0, le
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ule_sle:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ls
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, le
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ule i32 %s0, %s1
  %c1 = icmp sle i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ule_sgt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ule_sgt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #4, ls
; CHECK-SD-NEXT:    cset w0, gt
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ule_sgt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ls
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, gt
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ule i32 %s0, %s1
  %c1 = icmp sgt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ule_sge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ule_sge:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #8, ls
; CHECK-SD-NEXT:    cset w0, ge
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ule_sge:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ls
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ge
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ule i32 %s0, %s1
  %c1 = icmp sge i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ugt_eq(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ugt_eq:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, hi
; CHECK-SD-NEXT:    cset w0, eq
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ugt_eq:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, hi
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, eq
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ugt i32 %s0, %s1
  %c1 = icmp eq i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ugt_ne(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ugt_ne:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #4, hi
; CHECK-SD-NEXT:    cset w0, ne
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ugt_ne:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, hi
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ne
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ugt i32 %s0, %s1
  %c1 = icmp ne i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ugt_ult(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ugt_ult:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #2, hi
; CHECK-SD-NEXT:    cset w0, lo
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ugt_ult:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, hi
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, lo
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ugt i32 %s0, %s1
  %c1 = icmp ult i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ugt_ule(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ugt_ule:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #2, hi
; CHECK-SD-NEXT:    cset w0, ls
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ugt_ule:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, hi
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ls
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ugt i32 %s0, %s1
  %c1 = icmp ule i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ugt_ugt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ugt_ugt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, hi
; CHECK-SD-NEXT:    cset w0, hi
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ugt_ugt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, hi
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, hi
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ugt i32 %s0, %s1
  %c1 = icmp ugt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ugt_uge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ugt_uge:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, hi
; CHECK-SD-NEXT:    cset w0, hs
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ugt_uge:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, hi
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, hs
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ugt i32 %s0, %s1
  %c1 = icmp uge i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ugt_slt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ugt_slt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, hi
; CHECK-SD-NEXT:    cset w0, lt
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ugt_slt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, hi
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, lt
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ugt i32 %s0, %s1
  %c1 = icmp slt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ugt_sle(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ugt_sle:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, hi
; CHECK-SD-NEXT:    cset w0, le
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ugt_sle:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, hi
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, le
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ugt i32 %s0, %s1
  %c1 = icmp sle i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ugt_sgt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ugt_sgt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #4, hi
; CHECK-SD-NEXT:    cset w0, gt
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ugt_sgt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, hi
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, gt
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ugt i32 %s0, %s1
  %c1 = icmp sgt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_ugt_sge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_ugt_sge:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #8, hi
; CHECK-SD-NEXT:    cset w0, ge
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_ugt_sge:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, hi
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ge
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp ugt i32 %s0, %s1
  %c1 = icmp sge i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_uge_eq(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_uge_eq:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, hs
; CHECK-SD-NEXT:    cset w0, eq
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_uge_eq:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, hs
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, eq
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp uge i32 %s0, %s1
  %c1 = icmp eq i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_uge_ne(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_uge_ne:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #4, hs
; CHECK-SD-NEXT:    cset w0, ne
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_uge_ne:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, hs
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ne
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp uge i32 %s0, %s1
  %c1 = icmp ne i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_uge_ult(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_uge_ult:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #2, hs
; CHECK-SD-NEXT:    cset w0, lo
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_uge_ult:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, hs
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, lo
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp uge i32 %s0, %s1
  %c1 = icmp ult i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_uge_ule(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_uge_ule:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #2, hs
; CHECK-SD-NEXT:    cset w0, ls
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_uge_ule:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, hs
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ls
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp uge i32 %s0, %s1
  %c1 = icmp ule i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_uge_ugt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_uge_ugt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, hs
; CHECK-SD-NEXT:    cset w0, hi
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_uge_ugt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, hs
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, hi
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp uge i32 %s0, %s1
  %c1 = icmp ugt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_uge_uge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_uge_uge:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, hs
; CHECK-SD-NEXT:    cset w0, hs
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_uge_uge:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, hs
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, hs
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp uge i32 %s0, %s1
  %c1 = icmp uge i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_uge_slt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_uge_slt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, hs
; CHECK-SD-NEXT:    cset w0, lt
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_uge_slt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, hs
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, lt
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp uge i32 %s0, %s1
  %c1 = icmp slt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_uge_sle(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_uge_sle:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, hs
; CHECK-SD-NEXT:    cset w0, le
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_uge_sle:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, hs
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, le
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp uge i32 %s0, %s1
  %c1 = icmp sle i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_uge_sgt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_uge_sgt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #4, hs
; CHECK-SD-NEXT:    cset w0, gt
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_uge_sgt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, hs
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, gt
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp uge i32 %s0, %s1
  %c1 = icmp sgt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_uge_sge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_uge_sge:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #8, hs
; CHECK-SD-NEXT:    cset w0, ge
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_uge_sge:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, hs
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ge
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp uge i32 %s0, %s1
  %c1 = icmp sge i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_slt_eq(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_slt_eq:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, lt
; CHECK-SD-NEXT:    cset w0, eq
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_slt_eq:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, lt
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, eq
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp slt i32 %s0, %s1
  %c1 = icmp eq i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_slt_ne(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_slt_ne:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #4, lt
; CHECK-SD-NEXT:    cset w0, ne
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_slt_ne:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, lt
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ne
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp slt i32 %s0, %s1
  %c1 = icmp ne i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_slt_ult(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_slt_ult:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #2, lt
; CHECK-SD-NEXT:    cset w0, lo
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_slt_ult:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, lt
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, lo
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp slt i32 %s0, %s1
  %c1 = icmp ult i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_slt_ule(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_slt_ule:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #2, lt
; CHECK-SD-NEXT:    cset w0, ls
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_slt_ule:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, lt
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ls
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp slt i32 %s0, %s1
  %c1 = icmp ule i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_slt_ugt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_slt_ugt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, lt
; CHECK-SD-NEXT:    cset w0, hi
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_slt_ugt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, lt
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, hi
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp slt i32 %s0, %s1
  %c1 = icmp ugt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_slt_uge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_slt_uge:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, lt
; CHECK-SD-NEXT:    cset w0, hs
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_slt_uge:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, lt
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, hs
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp slt i32 %s0, %s1
  %c1 = icmp uge i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_slt_slt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_slt_slt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, lt
; CHECK-SD-NEXT:    cset w0, lt
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_slt_slt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, lt
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, lt
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp slt i32 %s0, %s1
  %c1 = icmp slt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_slt_sle(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_slt_sle:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, lt
; CHECK-SD-NEXT:    cset w0, le
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_slt_sle:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, lt
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, le
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp slt i32 %s0, %s1
  %c1 = icmp sle i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_slt_sgt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_slt_sgt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #4, lt
; CHECK-SD-NEXT:    cset w0, gt
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_slt_sgt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, lt
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, gt
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp slt i32 %s0, %s1
  %c1 = icmp sgt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_slt_sge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_slt_sge:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #8, lt
; CHECK-SD-NEXT:    cset w0, ge
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_slt_sge:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, lt
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ge
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp slt i32 %s0, %s1
  %c1 = icmp sge i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sle_eq(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sle_eq:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, le
; CHECK-SD-NEXT:    cset w0, eq
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sle_eq:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, le
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, eq
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sle i32 %s0, %s1
  %c1 = icmp eq i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sle_ne(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sle_ne:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #4, le
; CHECK-SD-NEXT:    cset w0, ne
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sle_ne:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, le
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ne
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sle i32 %s0, %s1
  %c1 = icmp ne i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sle_ult(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sle_ult:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #2, le
; CHECK-SD-NEXT:    cset w0, lo
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sle_ult:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, le
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, lo
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sle i32 %s0, %s1
  %c1 = icmp ult i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sle_ule(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sle_ule:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #2, le
; CHECK-SD-NEXT:    cset w0, ls
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sle_ule:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, le
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ls
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sle i32 %s0, %s1
  %c1 = icmp ule i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sle_ugt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sle_ugt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, le
; CHECK-SD-NEXT:    cset w0, hi
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sle_ugt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, le
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, hi
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sle i32 %s0, %s1
  %c1 = icmp ugt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sle_uge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sle_uge:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, le
; CHECK-SD-NEXT:    cset w0, hs
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sle_uge:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, le
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, hs
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sle i32 %s0, %s1
  %c1 = icmp uge i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sle_slt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sle_slt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, le
; CHECK-SD-NEXT:    cset w0, lt
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sle_slt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, le
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, lt
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sle i32 %s0, %s1
  %c1 = icmp slt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sle_sle(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sle_sle:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, le
; CHECK-SD-NEXT:    cset w0, le
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sle_sle:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, le
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, le
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sle i32 %s0, %s1
  %c1 = icmp sle i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sle_sgt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sle_sgt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #4, le
; CHECK-SD-NEXT:    cset w0, gt
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sle_sgt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, le
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, gt
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sle i32 %s0, %s1
  %c1 = icmp sgt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sle_sge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sle_sge:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #8, le
; CHECK-SD-NEXT:    cset w0, ge
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sle_sge:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, le
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ge
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sle i32 %s0, %s1
  %c1 = icmp sge i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sgt_eq(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sgt_eq:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, gt
; CHECK-SD-NEXT:    cset w0, eq
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sgt_eq:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, gt
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, eq
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sgt i32 %s0, %s1
  %c1 = icmp eq i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sgt_ne(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sgt_ne:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #4, gt
; CHECK-SD-NEXT:    cset w0, ne
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sgt_ne:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, gt
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ne
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sgt i32 %s0, %s1
  %c1 = icmp ne i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sgt_ult(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sgt_ult:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #2, gt
; CHECK-SD-NEXT:    cset w0, lo
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sgt_ult:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, gt
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, lo
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sgt i32 %s0, %s1
  %c1 = icmp ult i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sgt_ule(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sgt_ule:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #2, gt
; CHECK-SD-NEXT:    cset w0, ls
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sgt_ule:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, gt
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ls
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sgt i32 %s0, %s1
  %c1 = icmp ule i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sgt_ugt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sgt_ugt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, gt
; CHECK-SD-NEXT:    cset w0, hi
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sgt_ugt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, gt
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, hi
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sgt i32 %s0, %s1
  %c1 = icmp ugt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sgt_uge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sgt_uge:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, gt
; CHECK-SD-NEXT:    cset w0, hs
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sgt_uge:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, gt
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, hs
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sgt i32 %s0, %s1
  %c1 = icmp uge i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sgt_slt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sgt_slt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, gt
; CHECK-SD-NEXT:    cset w0, lt
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sgt_slt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, gt
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, lt
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sgt i32 %s0, %s1
  %c1 = icmp slt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sgt_sle(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sgt_sle:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, gt
; CHECK-SD-NEXT:    cset w0, le
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sgt_sle:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, gt
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, le
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sgt i32 %s0, %s1
  %c1 = icmp sle i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sgt_sgt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sgt_sgt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #4, gt
; CHECK-SD-NEXT:    cset w0, gt
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sgt_sgt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, gt
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, gt
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sgt i32 %s0, %s1
  %c1 = icmp sgt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sgt_sge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sgt_sge:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #8, gt
; CHECK-SD-NEXT:    cset w0, ge
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sgt_sge:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, gt
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ge
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sgt i32 %s0, %s1
  %c1 = icmp sge i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sge_eq(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sge_eq:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, ge
; CHECK-SD-NEXT:    cset w0, eq
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sge_eq:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ge
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, eq
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sge i32 %s0, %s1
  %c1 = icmp eq i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sge_ne(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sge_ne:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #4, ge
; CHECK-SD-NEXT:    cset w0, ne
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sge_ne:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ge
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ne
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sge i32 %s0, %s1
  %c1 = icmp ne i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sge_ult(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sge_ult:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #2, ge
; CHECK-SD-NEXT:    cset w0, lo
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sge_ult:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ge
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, lo
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sge i32 %s0, %s1
  %c1 = icmp ult i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sge_ule(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sge_ule:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #2, ge
; CHECK-SD-NEXT:    cset w0, ls
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sge_ule:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ge
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ls
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sge i32 %s0, %s1
  %c1 = icmp ule i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sge_ugt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sge_ugt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, ge
; CHECK-SD-NEXT:    cset w0, hi
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sge_ugt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ge
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, hi
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sge i32 %s0, %s1
  %c1 = icmp ugt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sge_uge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sge_uge:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, ge
; CHECK-SD-NEXT:    cset w0, hs
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sge_uge:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ge
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, hs
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sge i32 %s0, %s1
  %c1 = icmp uge i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sge_slt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sge_slt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, ge
; CHECK-SD-NEXT:    cset w0, lt
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sge_slt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ge
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, lt
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sge i32 %s0, %s1
  %c1 = icmp slt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sge_sle(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sge_sle:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #0, ge
; CHECK-SD-NEXT:    cset w0, le
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sge_sle:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ge
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, le
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sge i32 %s0, %s1
  %c1 = icmp sle i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sge_sgt(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sge_sgt:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #4, ge
; CHECK-SD-NEXT:    cset w0, gt
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sge_sgt:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ge
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, gt
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sge i32 %s0, %s1
  %c1 = icmp sgt i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @and_sge_sge(i32 %s0, i32 %s1, i32 %s2, i32 %s3) {
; CHECK-SD-LABEL: and_sge_sge:
; CHECK-SD:       // %bb.0: // %entry
; CHECK-SD-NEXT:    cmp w0, w1
; CHECK-SD-NEXT:    ccmp w2, w3, #8, ge
; CHECK-SD-NEXT:    cset w0, ge
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_sge_sge:
; CHECK-GI:       // %bb.0: // %entry
; CHECK-GI-NEXT:    cmp w0, w1
; CHECK-GI-NEXT:    cset w8, ge
; CHECK-GI-NEXT:    cmp w2, w3
; CHECK-GI-NEXT:    cset w9, ge
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret
entry:
  %c0 = icmp sge i32 %s0, %s1
  %c1 = icmp sge i32 %s2, %s3
  %a = and i1 %c0, %c1
  %z = zext i1 %a to i32
  ret i32 %z
}

define i32 @cmp_to_ands1(i32 %num) {
; CHECK-SD-LABEL: cmp_to_ands1:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    and w8, w0, #0xff
; CHECK-SD-NEXT:    tst w0, #0xfe
; CHECK-SD-NEXT:    csel w0, w8, wzr, ne
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: cmp_to_ands1:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    and w8, w0, #0xff
; CHECK-GI-NEXT:    cmp w8, #1
; CHECK-GI-NEXT:    csel w0, w8, wzr, hi
; CHECK-GI-NEXT:    ret
  %and = and i32 %num, 255
  %cmp = icmp ugt i32 %and, 1
  %r = select i1 %cmp, i32 %and, i32 0
  ret i32 %r
}

define i32 @cmp_to_ands2(i32 %num) {
; CHECK-SD-LABEL: cmp_to_ands2:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    and w8, w0, #0xfe
; CHECK-SD-NEXT:    tst w0, #0xc0
; CHECK-SD-NEXT:    csel w0, w8, wzr, ne
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: cmp_to_ands2:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    and w8, w0, #0xfe
; CHECK-GI-NEXT:    cmp w8, #63
; CHECK-GI-NEXT:    csel w0, w8, wzr, hi
; CHECK-GI-NEXT:    ret
  %and = and i32 %num, 254
  %cmp = icmp ugt i32 %and, 63
  %r = select i1 %cmp, i32 %and, i32 0
  ret i32 %r
}

define i32 @cmp_to_ands3(i32 %num, i32 %a) {
; CHECK-SD-LABEL: cmp_to_ands3:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    tst w0, #0x10
; CHECK-SD-NEXT:    csel w0, w1, wzr, ne
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: cmp_to_ands3:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    mov w8, #23 // =0x17
; CHECK-GI-NEXT:    and w8, w0, w8
; CHECK-GI-NEXT:    cmp w8, #7
; CHECK-GI-NEXT:    csel w0, w1, wzr, hi
; CHECK-GI-NEXT:    ret
  %and = and i32 %num, 23
  %cmp = icmp ugt i32 %and, 7
  %r = select i1 %cmp, i32 %a, i32 0
  ret i32 %r
}

define i32 @cmp_to_ands4(i32 %num, i32 %a) {
; CHECK-SD-LABEL: cmp_to_ands4:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    and w8, w0, #0x30
; CHECK-SD-NEXT:    tst w0, #0x20
; CHECK-SD-NEXT:    csel w0, w8, w1, eq
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: cmp_to_ands4:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    and w8, w0, #0x30
; CHECK-GI-NEXT:    cmp w8, #31
; CHECK-GI-NEXT:    csel w0, w8, w1, ls
; CHECK-GI-NEXT:    ret
  %and = and i32 %num, 48
  %cmp = icmp ule i32 %and, 31
  %r = select i1 %cmp, i32 %and, i32 %a
  ret i32 %r
}

define i32 @cmp_to_ands5(i32 %num, i32 %a) {
; CHECK-SD-LABEL: cmp_to_ands5:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    and w8, w0, #0xf8
; CHECK-SD-NEXT:    tst w0, #0xc0
; CHECK-SD-NEXT:    csel w0, w8, w1, eq
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: cmp_to_ands5:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    and w8, w0, #0xf8
; CHECK-GI-NEXT:    cmp w8, #64
; CHECK-GI-NEXT:    csel w0, w8, w1, lo
; CHECK-GI-NEXT:    ret
  %and = and i32 %num, 248
  %cmp = icmp ult i32 %and, 64
  %r = select i1 %cmp, i32 %and, i32 %a
  ret i32 %r
}

define i32 @cmp_to_ands6(i32 %num) {
; CHECK-SD-LABEL: cmp_to_ands6:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    and w8, w0, #0xfe
; CHECK-SD-NEXT:    tst w0, #0xf0
; CHECK-SD-NEXT:    csel w0, w8, wzr, ne
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: cmp_to_ands6:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    and w8, w0, #0xfe
; CHECK-GI-NEXT:    cmp w8, #16
; CHECK-GI-NEXT:    csel w0, w8, wzr, hs
; CHECK-GI-NEXT:    ret
  %and = and i32 %num, 254
  %cmp = icmp uge i32 %and, 16
  %r = select i1 %cmp, i32 %and, i32 0
  ret i32 %r
}

define i1 @and_fcmp(float %0, float %1) {
; CHECK-SD-LABEL: and_fcmp:
; CHECK-SD:       // %bb.0:
; CHECK-SD-NEXT:    fcmp s1, s1
; CHECK-SD-NEXT:    fccmp s0, s0, #0, vs
; CHECK-SD-NEXT:    cset w0, vs
; CHECK-SD-NEXT:    ret
;
; CHECK-GI-LABEL: and_fcmp:
; CHECK-GI:       // %bb.0:
; CHECK-GI-NEXT:    fcmp s0, #0.0
; CHECK-GI-NEXT:    cset w8, vs
; CHECK-GI-NEXT:    fcmp s1, #0.0
; CHECK-GI-NEXT:    cset w9, vs
; CHECK-GI-NEXT:    and w0, w8, w9
; CHECK-GI-NEXT:    ret

  %3 = fcmp uno float %0, 0.000000e+00
  %4 = fcmp uno float %1, 0.000000e+00
  %5 = and i1 %3, %4
  ret i1 %5
}


;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK: {{.*}}