From d4493dd1ed58ac3f1eab0c4ca6e363e2b15bfd1c Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Thu, 15 Dec 2022 11:41:22 -0500 Subject: [InstCombine] add nuw to any (1< ((1 << C) >> x) if C is bitwidth - 1 - if (match(Op0, m_One()) && - match(Op1, m_Sub(m_SpecificInt(BitWidth - 1), m_Value(X)))) - return BinaryOperator::CreateLShr( - ConstantInt::get(Ty, APInt::getSignMask(BitWidth)), X); + if (match(Op0, m_One())) { + // (1 << (C - x)) -> ((1 << C) >> x) if C is bitwidth - 1 + if (match(Op1, m_Sub(m_SpecificInt(BitWidth - 1), m_Value(X)))) + return BinaryOperator::CreateLShr( + ConstantInt::get(Ty, APInt::getSignMask(BitWidth)), X); + + // The only way to shift out the 1 is with an over-shift, and that would + // be poison either way. + if (!I.hasNoUnsignedWrap()) { + I.setHasNoUnsignedWrap(); + return &I; + } + } return nullptr; } diff --git a/llvm/test/Transforms/InstCombine/and-or-icmps.ll b/llvm/test/Transforms/InstCombine/and-or-icmps.ll index 7e76fd5..593ceff 100644 --- a/llvm/test/Transforms/InstCombine/and-or-icmps.ll +++ b/llvm/test/Transforms/InstCombine/and-or-icmps.ll @@ -1307,7 +1307,7 @@ define i1 @is_ascii_alphabetic_inverted(i32 %char) { define i1 @bitwise_and_bitwise_and_icmps(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @bitwise_and_bitwise_and_icmps( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i8 [[TMP2]], [[TMP1]] @@ -1328,7 +1328,7 @@ define i1 @bitwise_and_bitwise_and_icmps(i8 %x, i8 %y, i8 %z) { define i1 @bitwise_and_bitwise_and_icmps_comm1(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @bitwise_and_bitwise_and_icmps_comm1( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i8 [[TMP2]], [[TMP1]] @@ -1349,7 +1349,7 @@ define i1 @bitwise_and_bitwise_and_icmps_comm1(i8 %x, i8 %y, i8 %z) { define i1 @bitwise_and_bitwise_and_icmps_comm2(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @bitwise_and_bitwise_and_icmps_comm2( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i8 [[TMP2]], [[TMP1]] @@ -1370,7 +1370,7 @@ define i1 @bitwise_and_bitwise_and_icmps_comm2(i8 %x, i8 %y, i8 %z) { define i1 @bitwise_and_bitwise_and_icmps_comm3(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @bitwise_and_bitwise_and_icmps_comm3( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i8 [[TMP2]], [[TMP1]] @@ -1391,7 +1391,7 @@ define i1 @bitwise_and_bitwise_and_icmps_comm3(i8 %x, i8 %y, i8 %z) { define i1 @bitwise_and_logical_and_icmps(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @bitwise_and_logical_and_icmps( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i8 [[TMP2]], [[TMP1]] @@ -1412,7 +1412,7 @@ define i1 @bitwise_and_logical_and_icmps(i8 %x, i8 %y, i8 %z) { define i1 @bitwise_and_logical_and_icmps_comm1(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @bitwise_and_logical_and_icmps_comm1( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i8 [[TMP2]], [[TMP1]] @@ -1433,7 +1433,7 @@ define i1 @bitwise_and_logical_and_icmps_comm1(i8 %x, i8 %y, i8 %z) { define i1 @bitwise_and_logical_and_icmps_comm2(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @bitwise_and_logical_and_icmps_comm2( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = freeze i8 [[Z_SHIFT]] ; CHECK-NEXT: [[TMP2:%.*]] = or i8 [[TMP1]], 1 ; CHECK-NEXT: [[TMP3:%.*]] = and i8 [[TMP2]], [[X:%.*]] @@ -1455,7 +1455,7 @@ define i1 @bitwise_and_logical_and_icmps_comm2(i8 %x, i8 %y, i8 %z) { define i1 @bitwise_and_logical_and_icmps_comm3(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @bitwise_and_logical_and_icmps_comm3( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i8 [[TMP2]], [[TMP1]] @@ -1477,7 +1477,7 @@ define i1 @logical_and_bitwise_and_icmps(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @logical_and_bitwise_and_icmps( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 ; CHECK-NEXT: [[X_M1:%.*]] = and i8 [[X:%.*]], 1 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[Z_SHIFT]], [[X]] ; CHECK-NEXT: [[C2:%.*]] = icmp ne i8 [[X_M1]], 0 ; CHECK-NEXT: [[C3:%.*]] = icmp ne i8 [[X_M2]], 0 @@ -1500,7 +1500,7 @@ define i1 @logical_and_bitwise_and_icmps_comm1(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @logical_and_bitwise_and_icmps_comm1( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 ; CHECK-NEXT: [[X_M1:%.*]] = and i8 [[X:%.*]], 1 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[Z_SHIFT]], [[X]] ; CHECK-NEXT: [[C2:%.*]] = icmp ne i8 [[X_M1]], 0 ; CHECK-NEXT: [[C3:%.*]] = icmp ne i8 [[X_M2]], 0 @@ -1523,7 +1523,7 @@ define i1 @logical_and_bitwise_and_icmps_comm2(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @logical_and_bitwise_and_icmps_comm2( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 ; CHECK-NEXT: [[X_M1:%.*]] = and i8 [[X:%.*]], 1 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[Z_SHIFT]], [[X]] ; CHECK-NEXT: [[C2:%.*]] = icmp ne i8 [[X_M1]], 0 ; CHECK-NEXT: [[C3:%.*]] = icmp ne i8 [[X_M2]], 0 @@ -1546,7 +1546,7 @@ define i1 @logical_and_bitwise_and_icmps_comm3(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @logical_and_bitwise_and_icmps_comm3( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 ; CHECK-NEXT: [[X_M1:%.*]] = and i8 [[X:%.*]], 1 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[Z_SHIFT]], [[X]] ; CHECK-NEXT: [[C2:%.*]] = icmp ne i8 [[X_M1]], 0 ; CHECK-NEXT: [[C3:%.*]] = icmp ne i8 [[X_M2]], 0 @@ -1569,7 +1569,7 @@ define i1 @logical_and_logical_and_icmps(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @logical_and_logical_and_icmps( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 ; CHECK-NEXT: [[X_M1:%.*]] = and i8 [[X:%.*]], 1 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[Z_SHIFT]], [[X]] ; CHECK-NEXT: [[C2:%.*]] = icmp ne i8 [[X_M1]], 0 ; CHECK-NEXT: [[C3:%.*]] = icmp ne i8 [[X_M2]], 0 @@ -1592,7 +1592,7 @@ define i1 @logical_and_logical_and_icmps_comm1(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @logical_and_logical_and_icmps_comm1( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 ; CHECK-NEXT: [[X_M1:%.*]] = and i8 [[X:%.*]], 1 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[Z_SHIFT]], [[X]] ; CHECK-NEXT: [[C2:%.*]] = icmp ne i8 [[X_M1]], 0 ; CHECK-NEXT: [[C3:%.*]] = icmp ne i8 [[X_M2]], 0 @@ -1615,7 +1615,7 @@ define i1 @logical_and_logical_and_icmps_comm2(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @logical_and_logical_and_icmps_comm2( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 ; CHECK-NEXT: [[X_M1:%.*]] = and i8 [[X:%.*]], 1 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[Z_SHIFT]], [[X]] ; CHECK-NEXT: [[C2:%.*]] = icmp ne i8 [[X_M1]], 0 ; CHECK-NEXT: [[C3:%.*]] = icmp ne i8 [[X_M2]], 0 @@ -1637,7 +1637,7 @@ define i1 @logical_and_logical_and_icmps_comm2(i8 %x, i8 %y, i8 %z) { define i1 @logical_and_logical_and_icmps_comm3(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @logical_and_logical_and_icmps_comm3( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i8 [[TMP2]], [[TMP1]] @@ -1658,7 +1658,7 @@ define i1 @logical_and_logical_and_icmps_comm3(i8 %x, i8 %y, i8 %z) { define i1 @bitwise_or_bitwise_or_icmps(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @bitwise_or_bitwise_or_icmps( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i8 [[TMP2]], [[TMP1]] @@ -1679,7 +1679,7 @@ define i1 @bitwise_or_bitwise_or_icmps(i8 %x, i8 %y, i8 %z) { define i1 @bitwise_or_bitwise_or_icmps_comm1(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @bitwise_or_bitwise_or_icmps_comm1( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i8 [[TMP2]], [[TMP1]] @@ -1700,7 +1700,7 @@ define i1 @bitwise_or_bitwise_or_icmps_comm1(i8 %x, i8 %y, i8 %z) { define i1 @bitwise_or_bitwise_or_icmps_comm2(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @bitwise_or_bitwise_or_icmps_comm2( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i8 [[TMP2]], [[TMP1]] @@ -1721,7 +1721,7 @@ define i1 @bitwise_or_bitwise_or_icmps_comm2(i8 %x, i8 %y, i8 %z) { define i1 @bitwise_or_bitwise_or_icmps_comm3(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @bitwise_or_bitwise_or_icmps_comm3( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i8 [[TMP2]], [[TMP1]] @@ -1742,7 +1742,7 @@ define i1 @bitwise_or_bitwise_or_icmps_comm3(i8 %x, i8 %y, i8 %z) { define i1 @bitwise_or_logical_or_icmps(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @bitwise_or_logical_or_icmps( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i8 [[TMP2]], [[TMP1]] @@ -1763,7 +1763,7 @@ define i1 @bitwise_or_logical_or_icmps(i8 %x, i8 %y, i8 %z) { define i1 @bitwise_or_logical_or_icmps_comm1(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @bitwise_or_logical_or_icmps_comm1( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i8 [[TMP2]], [[TMP1]] @@ -1784,7 +1784,7 @@ define i1 @bitwise_or_logical_or_icmps_comm1(i8 %x, i8 %y, i8 %z) { define i1 @bitwise_or_logical_or_icmps_comm2(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @bitwise_or_logical_or_icmps_comm2( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = freeze i8 [[Z_SHIFT]] ; CHECK-NEXT: [[TMP2:%.*]] = or i8 [[TMP1]], 1 ; CHECK-NEXT: [[TMP3:%.*]] = and i8 [[TMP2]], [[X:%.*]] @@ -1806,7 +1806,7 @@ define i1 @bitwise_or_logical_or_icmps_comm2(i8 %x, i8 %y, i8 %z) { define i1 @bitwise_or_logical_or_icmps_comm3(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @bitwise_or_logical_or_icmps_comm3( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i8 [[TMP2]], [[TMP1]] @@ -1828,7 +1828,7 @@ define i1 @logical_or_bitwise_or_icmps(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @logical_or_bitwise_or_icmps( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 ; CHECK-NEXT: [[X_M1:%.*]] = and i8 [[X:%.*]], 1 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[Z_SHIFT]], [[X]] ; CHECK-NEXT: [[C2:%.*]] = icmp eq i8 [[X_M1]], 0 ; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[X_M2]], 0 @@ -1851,7 +1851,7 @@ define i1 @logical_or_bitwise_or_icmps_comm1(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @logical_or_bitwise_or_icmps_comm1( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 ; CHECK-NEXT: [[X_M1:%.*]] = and i8 [[X:%.*]], 1 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[Z_SHIFT]], [[X]] ; CHECK-NEXT: [[C2:%.*]] = icmp eq i8 [[X_M1]], 0 ; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[X_M2]], 0 @@ -1874,7 +1874,7 @@ define i1 @logical_or_bitwise_or_icmps_comm2(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @logical_or_bitwise_or_icmps_comm2( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 ; CHECK-NEXT: [[X_M1:%.*]] = and i8 [[X:%.*]], 1 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[Z_SHIFT]], [[X]] ; CHECK-NEXT: [[C2:%.*]] = icmp eq i8 [[X_M1]], 0 ; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[X_M2]], 0 @@ -1897,7 +1897,7 @@ define i1 @logical_or_bitwise_or_icmps_comm3(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @logical_or_bitwise_or_icmps_comm3( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 ; CHECK-NEXT: [[X_M1:%.*]] = and i8 [[X:%.*]], 1 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[Z_SHIFT]], [[X]] ; CHECK-NEXT: [[C2:%.*]] = icmp eq i8 [[X_M1]], 0 ; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[X_M2]], 0 @@ -1920,7 +1920,7 @@ define i1 @logical_or_logical_or_icmps(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @logical_or_logical_or_icmps( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 ; CHECK-NEXT: [[X_M1:%.*]] = and i8 [[X:%.*]], 1 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[Z_SHIFT]], [[X]] ; CHECK-NEXT: [[C2:%.*]] = icmp eq i8 [[X_M1]], 0 ; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[X_M2]], 0 @@ -1943,7 +1943,7 @@ define i1 @logical_or_logical_or_icmps_comm1(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @logical_or_logical_or_icmps_comm1( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 ; CHECK-NEXT: [[X_M1:%.*]] = and i8 [[X:%.*]], 1 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[Z_SHIFT]], [[X]] ; CHECK-NEXT: [[C2:%.*]] = icmp eq i8 [[X_M1]], 0 ; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[X_M2]], 0 @@ -1966,7 +1966,7 @@ define i1 @logical_or_logical_or_icmps_comm2(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @logical_or_logical_or_icmps_comm2( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 ; CHECK-NEXT: [[X_M1:%.*]] = and i8 [[X:%.*]], 1 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[X_M2:%.*]] = and i8 [[Z_SHIFT]], [[X]] ; CHECK-NEXT: [[C2:%.*]] = icmp eq i8 [[X_M1]], 0 ; CHECK-NEXT: [[C3:%.*]] = icmp eq i8 [[X_M2]], 0 @@ -1988,7 +1988,7 @@ define i1 @logical_or_logical_or_icmps_comm2(i8 %x, i8 %y, i8 %z) { define i1 @logical_or_logical_or_icmps_comm3(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @logical_or_logical_or_icmps_comm3( ; CHECK-NEXT: [[C1:%.*]] = icmp eq i8 [[Y:%.*]], 42 -; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Z_SHIFT:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or i8 [[Z_SHIFT]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = and i8 [[TMP1]], [[X:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i8 [[TMP2]], [[TMP1]] diff --git a/llvm/test/Transforms/InstCombine/and2.ll b/llvm/test/Transforms/InstCombine/and2.ll index 9bb0281..30fe059 100644 --- a/llvm/test/Transforms/InstCombine/and2.ll +++ b/llvm/test/Transforms/InstCombine/and2.ll @@ -144,9 +144,9 @@ define i8 @and1_shl1_is_cmp_eq_0(i8 %x) { define i8 @and1_shl1_is_cmp_eq_0_multiuse(i8 %x) { ; CHECK-LABEL: @and1_shl1_is_cmp_eq_0_multiuse( -; CHECK-NEXT: [[SH:%.*]] = shl i8 1, [[X:%.*]] +; CHECK-NEXT: [[SH:%.*]] = shl nuw i8 1, [[X:%.*]] ; CHECK-NEXT: [[AND:%.*]] = and i8 [[SH]], 1 -; CHECK-NEXT: [[ADD:%.*]] = add i8 [[SH]], [[AND]] +; CHECK-NEXT: [[ADD:%.*]] = add nuw i8 [[SH]], [[AND]] ; CHECK-NEXT: ret i8 [[ADD]] ; %sh = shl i8 1, %x diff --git a/llvm/test/Transforms/InstCombine/apint-shl-trunc.ll b/llvm/test/Transforms/InstCombine/apint-shl-trunc.ll index 3d31a27..2d72a4f 100644 --- a/llvm/test/Transforms/InstCombine/apint-shl-trunc.ll +++ b/llvm/test/Transforms/InstCombine/apint-shl-trunc.ll @@ -3,7 +3,7 @@ define i1 @test0(i39 %X, i39 %A) { ; CHECK-LABEL: @test0( -; CHECK-NEXT: [[TMP1:%.*]] = shl i39 1, [[A:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = shl nuw i39 1, [[A:%.*]] ; CHECK-NEXT: [[TMP2:%.*]] = and i39 [[TMP1]], [[X:%.*]] ; CHECK-NEXT: [[D:%.*]] = icmp ne i39 [[TMP2]], 0 ; CHECK-NEXT: ret i1 [[D]] @@ -15,7 +15,7 @@ define i1 @test0(i39 %X, i39 %A) { define i1 @test1(i799 %X, i799 %A) { ; CHECK-LABEL: @test1( -; CHECK-NEXT: [[TMP1:%.*]] = shl i799 1, [[A:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = shl nuw i799 1, [[A:%.*]] ; CHECK-NEXT: [[TMP2:%.*]] = and i799 [[TMP1]], [[X:%.*]] ; CHECK-NEXT: [[D:%.*]] = icmp ne i799 [[TMP2]], 0 ; CHECK-NEXT: ret i1 [[D]] diff --git a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v2-and-icmp-eq-to-icmp-ule.ll b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v2-and-icmp-eq-to-icmp-ule.ll index 1893c73..2c2afff 100644 --- a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v2-and-icmp-eq-to-icmp-ule.ll +++ b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v2-and-icmp-eq-to-icmp-ule.ll @@ -268,7 +268,7 @@ define i1 @n0(i8 %x, i8 %y, i8 %notx) { define i1 @n1(i8 %x, i8 %y) { ; CHECK-LABEL: @n1( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Y:%.*]] ; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 ; CHECK-NEXT: [[T2:%.*]] = and i8 [[T1]], [[X:%.*]] ; CHECK-NEXT: [[RET:%.*]] = icmp eq i8 [[T2]], [[X]] diff --git a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v2-and-icmp-ne-to-icmp-ugt.ll b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v2-and-icmp-ne-to-icmp-ugt.ll index 835e7dd..1b0947b 100644 --- a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v2-and-icmp-ne-to-icmp-ugt.ll +++ b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v2-and-icmp-ne-to-icmp-ugt.ll @@ -268,7 +268,7 @@ define i1 @n0(i8 %x, i8 %y, i8 %notx) { define i1 @n1(i8 %x, i8 %y) { ; CHECK-LABEL: @n1( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Y:%.*]] ; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 ; CHECK-NEXT: [[T2:%.*]] = and i8 [[T1]], [[X:%.*]] ; CHECK-NEXT: [[RET:%.*]] = icmp ne i8 [[T2]], [[X]] diff --git a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v3-and-icmp-eq-to-icmp-ule.ll b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v3-and-icmp-eq-to-icmp-ule.ll index 82f1abf..152a52a 100644 --- a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v3-and-icmp-eq-to-icmp-ule.ll +++ b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v3-and-icmp-eq-to-icmp-ule.ll @@ -22,7 +22,7 @@ declare void @use3i8(<3 x i8>) define i1 @p0(i8 %x, i8 %y) { ; CHECK-LABEL: @p0( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Y:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr i8 [[X:%.*]], [[Y]] ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i8 [[X_HIGHBITS]], 0 @@ -42,7 +42,7 @@ define i1 @p0(i8 %x, i8 %y) { define <2 x i1> @p1_vec(<2 x i8> %x, <2 x i8> %y) { ; CHECK-LABEL: @p1_vec( -; CHECK-NEXT: [[T0:%.*]] = shl <2 x i8> , [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw <2 x i8> , [[Y:%.*]] ; CHECK-NEXT: call void @use2i8(<2 x i8> [[T0]]) ; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr <2 x i8> [[X:%.*]], [[Y]] ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <2 x i8> [[X_HIGHBITS]], zeroinitializer @@ -58,7 +58,7 @@ define <2 x i1> @p1_vec(<2 x i8> %x, <2 x i8> %y) { define <3 x i1> @p2_vec_undef0(<3 x i8> %x, <3 x i8> %y) { ; CHECK-LABEL: @p2_vec_undef0( -; CHECK-NEXT: [[T0:%.*]] = shl <3 x i8> , [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> , [[Y:%.*]] ; CHECK-NEXT: call void @use3i8(<3 x i8> [[T0]]) ; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr <3 x i8> [[X:%.*]], [[Y]] ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <3 x i8> [[X_HIGHBITS]], zeroinitializer @@ -74,7 +74,7 @@ define <3 x i1> @p2_vec_undef0(<3 x i8> %x, <3 x i8> %y) { define <3 x i1> @p3_vec_undef0(<3 x i8> %x, <3 x i8> %y) { ; CHECK-LABEL: @p3_vec_undef0( -; CHECK-NEXT: [[T0:%.*]] = shl <3 x i8> , [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> , [[Y:%.*]] ; CHECK-NEXT: call void @use3i8(<3 x i8> [[T0]]) ; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr <3 x i8> [[X:%.*]], [[Y]] ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <3 x i8> [[X_HIGHBITS]], zeroinitializer @@ -90,7 +90,7 @@ define <3 x i1> @p3_vec_undef0(<3 x i8> %x, <3 x i8> %y) { define <3 x i1> @p4_vec_undef2(<3 x i8> %x, <3 x i8> %y) { ; CHECK-LABEL: @p4_vec_undef2( -; CHECK-NEXT: [[T0:%.*]] = shl <3 x i8> , [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> , [[Y:%.*]] ; CHECK-NEXT: call void @use3i8(<3 x i8> [[T0]]) ; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr <3 x i8> [[X:%.*]], [[Y]] ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq <3 x i8> [[X_HIGHBITS]], zeroinitializer @@ -112,7 +112,7 @@ declare i8 @gen8() define i1 @c0(i8 %y) { ; CHECK-LABEL: @c0( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Y:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[X:%.*]] = call i8 @gen8() ; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr i8 [[X]], [[Y]] @@ -130,7 +130,7 @@ define i1 @c0(i8 %y) { define i1 @c1(i8 %y) { ; CHECK-LABEL: @c1( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Y:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[X:%.*]] = call i8 @gen8() ; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr i8 [[X]], [[Y]] @@ -148,7 +148,7 @@ define i1 @c1(i8 %y) { define i1 @c2(i8 %y) { ; CHECK-LABEL: @c2( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Y:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[X:%.*]] = call i8 @gen8() ; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr i8 [[X]], [[Y]] @@ -170,7 +170,7 @@ define i1 @c2(i8 %y) { define i1 @oneuse0(i8 %x, i8 %y) { ; CHECK-LABEL: @oneuse0( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Y:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0]], -1 ; CHECK-NEXT: call void @use8(i8 [[T1]]) @@ -188,7 +188,7 @@ define i1 @oneuse0(i8 %x, i8 %y) { define i1 @oneuse1(i8 %x, i8 %y) { ; CHECK-LABEL: @oneuse1( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Y:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0]], -1 ; CHECK-NEXT: [[T2:%.*]] = and i8 [[T1]], [[X:%.*]] @@ -207,7 +207,7 @@ define i1 @oneuse1(i8 %x, i8 %y) { define i1 @oneuse2(i8 %x, i8 %y) { ; CHECK-LABEL: @oneuse2( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Y:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0]], -1 ; CHECK-NEXT: call void @use8(i8 [[T1]]) @@ -232,7 +232,7 @@ define i1 @oneuse2(i8 %x, i8 %y) { define i1 @n0(i8 %x, i8 %y, i8 %notx) { ; CHECK-LABEL: @n0( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Y:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0]], -1 ; CHECK-NEXT: [[T2:%.*]] = and i8 [[T1]], [[X:%.*]] @@ -266,9 +266,9 @@ define i1 @n1(i8 %x, i8 %y) { define i1 @n2(i8 %x, i8 %y) { ; CHECK-LABEL: @n2( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Y:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) -; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0]], 1 +; CHECK-NEXT: [[T1:%.*]] = add nuw i8 [[T0]], 1 ; CHECK-NEXT: [[T2:%.*]] = and i8 [[T1]], [[X:%.*]] ; CHECK-NEXT: [[RET:%.*]] = icmp eq i8 [[T2]], [[X]] ; CHECK-NEXT: ret i1 [[RET]] diff --git a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v3-and-icmp-ne-to-icmp-ugt.ll b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v3-and-icmp-ne-to-icmp-ugt.ll index 4dd3af3..f1d1a06 100644 --- a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v3-and-icmp-ne-to-icmp-ugt.ll +++ b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v3-and-icmp-ne-to-icmp-ugt.ll @@ -22,7 +22,7 @@ declare void @use3i8(<3 x i8>) define i1 @p0(i8 %x, i8 %y) { ; CHECK-LABEL: @p0( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Y:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr i8 [[X:%.*]], [[Y]] ; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i8 [[X_HIGHBITS]], 0 @@ -42,7 +42,7 @@ define i1 @p0(i8 %x, i8 %y) { define <2 x i1> @p1_vec(<2 x i8> %x, <2 x i8> %y) { ; CHECK-LABEL: @p1_vec( -; CHECK-NEXT: [[T0:%.*]] = shl <2 x i8> , [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw <2 x i8> , [[Y:%.*]] ; CHECK-NEXT: call void @use2i8(<2 x i8> [[T0]]) ; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr <2 x i8> [[X:%.*]], [[Y]] ; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <2 x i8> [[X_HIGHBITS]], zeroinitializer @@ -58,7 +58,7 @@ define <2 x i1> @p1_vec(<2 x i8> %x, <2 x i8> %y) { define <3 x i1> @p2_vec_undef0(<3 x i8> %x, <3 x i8> %y) { ; CHECK-LABEL: @p2_vec_undef0( -; CHECK-NEXT: [[T0:%.*]] = shl <3 x i8> , [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> , [[Y:%.*]] ; CHECK-NEXT: call void @use3i8(<3 x i8> [[T0]]) ; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr <3 x i8> [[X:%.*]], [[Y]] ; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <3 x i8> [[X_HIGHBITS]], zeroinitializer @@ -74,7 +74,7 @@ define <3 x i1> @p2_vec_undef0(<3 x i8> %x, <3 x i8> %y) { define <3 x i1> @p3_vec_undef0(<3 x i8> %x, <3 x i8> %y) { ; CHECK-LABEL: @p3_vec_undef0( -; CHECK-NEXT: [[T0:%.*]] = shl <3 x i8> , [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> , [[Y:%.*]] ; CHECK-NEXT: call void @use3i8(<3 x i8> [[T0]]) ; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr <3 x i8> [[X:%.*]], [[Y]] ; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <3 x i8> [[X_HIGHBITS]], zeroinitializer @@ -90,7 +90,7 @@ define <3 x i1> @p3_vec_undef0(<3 x i8> %x, <3 x i8> %y) { define <3 x i1> @p4_vec_undef2(<3 x i8> %x, <3 x i8> %y) { ; CHECK-LABEL: @p4_vec_undef2( -; CHECK-NEXT: [[T0:%.*]] = shl <3 x i8> , [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> , [[Y:%.*]] ; CHECK-NEXT: call void @use3i8(<3 x i8> [[T0]]) ; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr <3 x i8> [[X:%.*]], [[Y]] ; CHECK-NEXT: [[TMP1:%.*]] = icmp ne <3 x i8> [[X_HIGHBITS]], zeroinitializer @@ -112,7 +112,7 @@ declare i8 @gen8() define i1 @c0(i8 %y) { ; CHECK-LABEL: @c0( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Y:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[X:%.*]] = call i8 @gen8() ; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr i8 [[X]], [[Y]] @@ -130,7 +130,7 @@ define i1 @c0(i8 %y) { define i1 @c1(i8 %y) { ; CHECK-LABEL: @c1( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Y:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[X:%.*]] = call i8 @gen8() ; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr i8 [[X]], [[Y]] @@ -148,7 +148,7 @@ define i1 @c1(i8 %y) { define i1 @c2(i8 %y) { ; CHECK-LABEL: @c2( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Y:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[X:%.*]] = call i8 @gen8() ; CHECK-NEXT: [[X_HIGHBITS:%.*]] = lshr i8 [[X]], [[Y]] @@ -170,7 +170,7 @@ define i1 @c2(i8 %y) { define i1 @oneuse0(i8 %x, i8 %y) { ; CHECK-LABEL: @oneuse0( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Y:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0]], -1 ; CHECK-NEXT: call void @use8(i8 [[T1]]) @@ -188,7 +188,7 @@ define i1 @oneuse0(i8 %x, i8 %y) { define i1 @oneuse1(i8 %x, i8 %y) { ; CHECK-LABEL: @oneuse1( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Y:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0]], -1 ; CHECK-NEXT: [[T2:%.*]] = and i8 [[T1]], [[X:%.*]] @@ -207,7 +207,7 @@ define i1 @oneuse1(i8 %x, i8 %y) { define i1 @oneuse2(i8 %x, i8 %y) { ; CHECK-LABEL: @oneuse2( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Y:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0]], -1 ; CHECK-NEXT: call void @use8(i8 [[T1]]) @@ -232,7 +232,7 @@ define i1 @oneuse2(i8 %x, i8 %y) { define i1 @n0(i8 %x, i8 %y, i8 %notx) { ; CHECK-LABEL: @n0( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Y:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0]], -1 ; CHECK-NEXT: [[T2:%.*]] = and i8 [[T1]], [[X:%.*]] @@ -266,9 +266,9 @@ define i1 @n1(i8 %x, i8 %y) { define i1 @n2(i8 %x, i8 %y) { ; CHECK-LABEL: @n2( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Y:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) -; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0]], 1 +; CHECK-NEXT: [[T1:%.*]] = add nuw i8 [[T0]], 1 ; CHECK-NEXT: [[T2:%.*]] = and i8 [[T1]], [[X:%.*]] ; CHECK-NEXT: [[RET:%.*]] = icmp ne i8 [[T2]], [[X]] ; CHECK-NEXT: ret i1 [[RET]] diff --git a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v4-and-icmp-eq-to-icmp-ule.ll b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v4-and-icmp-eq-to-icmp-ule.ll index 5bc2754..d110c01 100644 --- a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v4-and-icmp-eq-to-icmp-ule.ll +++ b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v4-and-icmp-eq-to-icmp-ule.ll @@ -215,12 +215,10 @@ define i1 @n0(i8 %x, i8 %y, i8 %notx) { define i1 @n1(i8 %x, i8 %y) { ; CHECK-LABEL: @n1( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Y:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) -; CHECK-NEXT: [[T1:%.*]] = lshr i8 [[T0]], [[Y]] -; CHECK-NEXT: [[T2:%.*]] = and i8 [[T1]], [[X:%.*]] -; CHECK-NEXT: [[RET:%.*]] = icmp eq i8 [[T2]], [[X]] -; CHECK-NEXT: ret i1 [[RET]] +; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i8 [[X:%.*]], 2 +; CHECK-NEXT: ret i1 [[TMP1]] ; %t0 = shl i8 1, %y ; not -1 call void @use8(i8 %t0) diff --git a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v4-and-icmp-ne-to-icmp-ugt.ll b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v4-and-icmp-ne-to-icmp-ugt.ll index 6b539b1..b7e5d08 100644 --- a/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v4-and-icmp-ne-to-icmp-ugt.ll +++ b/llvm/test/Transforms/InstCombine/canonicalize-low-bit-mask-v4-and-icmp-ne-to-icmp-ugt.ll @@ -215,12 +215,10 @@ define i1 @n0(i8 %x, i8 %y, i8 %notx) { define i1 @n1(i8 %x, i8 %y) { ; CHECK-LABEL: @n1( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Y:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) -; CHECK-NEXT: [[T1:%.*]] = lshr i8 [[T0]], [[Y]] -; CHECK-NEXT: [[T2:%.*]] = and i8 [[T1]], [[X:%.*]] -; CHECK-NEXT: [[RET:%.*]] = icmp ne i8 [[T2]], [[X]] -; CHECK-NEXT: ret i1 [[RET]] +; CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i8 [[X:%.*]], 1 +; CHECK-NEXT: ret i1 [[TMP1]] ; %t0 = shl i8 1, %y ; not -1 call void @use8(i8 %t0) diff --git a/llvm/test/Transforms/InstCombine/conditional-variable-length-signext-after-high-bit-extract.ll b/llvm/test/Transforms/InstCombine/conditional-variable-length-signext-after-high-bit-extract.ll index 15571df..cdcd8a8 100644 --- a/llvm/test/Transforms/InstCombine/conditional-variable-length-signext-after-high-bit-extract.ll +++ b/llvm/test/Transforms/InstCombine/conditional-variable-length-signext-after-high-bit-extract.ll @@ -81,7 +81,7 @@ define i32 @t1_notrunc_sub(i32 %data, i32 %nbits) { ; CHECK-NEXT: [[LOW_BITS_TO_SKIP:%.*]] = sub i32 32, [[NBITS:%.*]] ; CHECK-NEXT: [[HIGH_BITS_EXTRACTED:%.*]] = lshr i32 [[DATA:%.*]], [[LOW_BITS_TO_SKIP]] ; CHECK-NEXT: [[SHOULD_SIGNEXT:%.*]] = icmp slt i32 [[DATA]], 0 -; CHECK-NEXT: [[HIGHER_BIT_AFTER_SIGNBIT:%.*]] = shl i32 1, [[NBITS]] +; CHECK-NEXT: [[HIGHER_BIT_AFTER_SIGNBIT:%.*]] = shl nuw i32 1, [[NBITS]] ; CHECK-NEXT: [[MAGIC:%.*]] = select i1 [[SHOULD_SIGNEXT]], i32 [[HIGHER_BIT_AFTER_SIGNBIT]], i32 0 ; CHECK-NEXT: call void @use32(i32 [[LOW_BITS_TO_SKIP]]) ; CHECK-NEXT: call void @use32(i32 [[HIGH_BITS_EXTRACTED]]) @@ -188,7 +188,7 @@ define i32 @t3_trunc_sub(i64 %data, i32 %nbits) { ; CHECK-NEXT: [[HIGH_BITS_EXTRACTED_WIDE:%.*]] = lshr i64 [[DATA:%.*]], [[LOW_BITS_TO_SKIP_WIDE]] ; CHECK-NEXT: [[HIGH_BITS_EXTRACTED:%.*]] = trunc i64 [[HIGH_BITS_EXTRACTED_WIDE]] to i32 ; CHECK-NEXT: [[SHOULD_SIGNEXT:%.*]] = icmp slt i64 [[DATA]], 0 -; CHECK-NEXT: [[HIGHER_BIT_AFTER_SIGNBIT:%.*]] = shl i32 1, [[NBITS]] +; CHECK-NEXT: [[HIGHER_BIT_AFTER_SIGNBIT:%.*]] = shl nuw i32 1, [[NBITS]] ; CHECK-NEXT: call void @use32(i32 [[LOW_BITS_TO_SKIP]]) ; CHECK-NEXT: call void @use64(i64 [[LOW_BITS_TO_SKIP_WIDE]]) ; CHECK-NEXT: call void @use64(i64 [[HIGH_BITS_EXTRACTED_WIDE]]) @@ -548,7 +548,7 @@ define i32 @t13_sub_zext_of_magic(i32 %data, i8 %nbits) { ; CHECK-NEXT: [[HIGH_BITS_EXTRACTED:%.*]] = lshr i32 [[DATA:%.*]], [[LOW_BITS_TO_SKIP]] ; CHECK-NEXT: [[SHOULD_SIGNEXT:%.*]] = icmp slt i32 [[DATA]], 0 ; CHECK-NEXT: [[NBITS_16BIT:%.*]] = zext i8 [[NBITS]] to i16 -; CHECK-NEXT: [[ALL_BITS_EXCEPT_LOW_NBITS:%.*]] = shl i16 1, [[NBITS_16BIT]] +; CHECK-NEXT: [[ALL_BITS_EXCEPT_LOW_NBITS:%.*]] = shl nuw i16 1, [[NBITS_16BIT]] ; CHECK-NEXT: [[MAGIC:%.*]] = select i1 [[SHOULD_SIGNEXT]], i16 [[ALL_BITS_EXCEPT_LOW_NBITS]], i16 0 ; CHECK-NEXT: [[MAGIC_WIDE:%.*]] = zext i16 [[MAGIC]] to i32 ; CHECK-NEXT: call void @use32(i32 [[NBITS_32BIT]]) @@ -634,7 +634,7 @@ define i32 @t15_sub_zext_of_shl(i32 %data, i8 %nbits) { ; CHECK-NEXT: [[HIGH_BITS_EXTRACTED:%.*]] = lshr i32 [[DATA:%.*]], [[LOW_BITS_TO_SKIP]] ; CHECK-NEXT: [[SHOULD_SIGNEXT:%.*]] = icmp slt i32 [[DATA]], 0 ; CHECK-NEXT: [[NBITS_16BIT:%.*]] = zext i8 [[NBITS]] to i16 -; CHECK-NEXT: [[ALL_BITS_EXCEPT_LOW_NBITS:%.*]] = shl i16 1, [[NBITS_16BIT]] +; CHECK-NEXT: [[ALL_BITS_EXCEPT_LOW_NBITS:%.*]] = shl nuw i16 1, [[NBITS_16BIT]] ; CHECK-NEXT: [[ALL_BITS_EXCEPT_LOW_NBITS_WIDE:%.*]] = zext i16 [[ALL_BITS_EXCEPT_LOW_NBITS]] to i32 ; CHECK-NEXT: [[MAGIC:%.*]] = select i1 [[SHOULD_SIGNEXT]], i32 [[ALL_BITS_EXCEPT_LOW_NBITS_WIDE]], i32 0 ; CHECK-NEXT: call void @use32(i32 [[NBITS_32BIT]]) @@ -708,7 +708,7 @@ define i32 @n17_add(i32 %data, i32 %nbits) { ; CHECK-NEXT: [[LOW_BITS_TO_SKIP:%.*]] = sub i32 32, [[NBITS:%.*]] ; CHECK-NEXT: [[HIGH_BITS_EXTRACTED:%.*]] = lshr i32 [[DATA:%.*]], [[LOW_BITS_TO_SKIP]] ; CHECK-NEXT: [[SHOULD_SIGNEXT:%.*]] = icmp slt i32 [[DATA]], 0 -; CHECK-NEXT: [[ALL_BITS_EXCEPT_LOW_NBITS:%.*]] = shl i32 1, [[NBITS]] +; CHECK-NEXT: [[ALL_BITS_EXCEPT_LOW_NBITS:%.*]] = shl nuw i32 1, [[NBITS]] ; CHECK-NEXT: [[MAGIC:%.*]] = select i1 [[SHOULD_SIGNEXT]], i32 [[ALL_BITS_EXCEPT_LOW_NBITS]], i32 0 ; CHECK-NEXT: call void @use32(i32 [[LOW_BITS_TO_SKIP]]) ; CHECK-NEXT: call void @use32(i32 [[HIGH_BITS_EXTRACTED]]) @@ -933,7 +933,7 @@ define i32 @n24(i32 %data, i32 %nbits) { ; CHECK-NEXT: [[LOW_BITS_TO_SKIP:%.*]] = sub i32 32, [[NBITS:%.*]] ; CHECK-NEXT: [[HIGH_BITS_EXTRACTED:%.*]] = lshr i32 [[DATA:%.*]], [[LOW_BITS_TO_SKIP]] ; CHECK-NEXT: [[SHOULD_SIGNEXT:%.*]] = icmp slt i32 [[DATA]], 0 -; CHECK-NEXT: [[HIGHER_BIT_AFTER_SIGNBIT:%.*]] = shl i32 1, [[NBITS]] +; CHECK-NEXT: [[HIGHER_BIT_AFTER_SIGNBIT:%.*]] = shl nuw i32 1, [[NBITS]] ; CHECK-NEXT: [[MAGIC:%.*]] = select i1 [[SHOULD_SIGNEXT]], i32 [[HIGHER_BIT_AFTER_SIGNBIT]], i32 0 ; CHECK-NEXT: call void @use32(i32 [[LOW_BITS_TO_SKIP]]) ; CHECK-NEXT: call void @use32(i32 [[HIGH_BITS_EXTRACTED]]) @@ -1071,7 +1071,7 @@ define i32 @n28_sub_sext_of_magic(i32 %data, i8 %nbits) { ; CHECK-NEXT: [[HIGH_BITS_EXTRACTED:%.*]] = lshr i32 [[DATA:%.*]], [[LOW_BITS_TO_SKIP]] ; CHECK-NEXT: [[SHOULD_SIGNEXT:%.*]] = icmp slt i32 [[DATA]], 0 ; CHECK-NEXT: [[NBITS_16BIT:%.*]] = zext i8 [[NBITS]] to i16 -; CHECK-NEXT: [[ALL_BITS_EXCEPT_LOW_NBITS:%.*]] = shl i16 1, [[NBITS_16BIT]] +; CHECK-NEXT: [[ALL_BITS_EXCEPT_LOW_NBITS:%.*]] = shl nuw i16 1, [[NBITS_16BIT]] ; CHECK-NEXT: [[MAGIC:%.*]] = select i1 [[SHOULD_SIGNEXT]], i16 [[ALL_BITS_EXCEPT_LOW_NBITS]], i16 0 ; CHECK-NEXT: [[MAGIC_WIDE:%.*]] = sext i16 [[MAGIC]] to i32 ; CHECK-NEXT: call void @use32(i32 [[NBITS_32BIT]]) @@ -1112,7 +1112,7 @@ define i32 @n290_or_with_wrong_magic(i32 %data, i32 %nbits) { ; CHECK-NEXT: [[LOW_BITS_TO_SKIP:%.*]] = sub i32 32, [[NBITS:%.*]] ; CHECK-NEXT: [[HIGH_BITS_EXTRACTED:%.*]] = lshr i32 [[DATA:%.*]], [[LOW_BITS_TO_SKIP]] ; CHECK-NEXT: [[SHOULD_SIGNEXT:%.*]] = icmp slt i32 [[DATA]], 0 -; CHECK-NEXT: [[ALL_BITS_EXCEPT_LOW_NBITS:%.*]] = shl i32 1, [[NBITS]] +; CHECK-NEXT: [[ALL_BITS_EXCEPT_LOW_NBITS:%.*]] = shl nuw i32 1, [[NBITS]] ; CHECK-NEXT: [[MAGIC:%.*]] = select i1 [[SHOULD_SIGNEXT]], i32 [[ALL_BITS_EXCEPT_LOW_NBITS]], i32 0 ; CHECK-NEXT: call void @use32(i32 [[LOW_BITS_TO_SKIP]]) ; CHECK-NEXT: call void @use32(i32 [[HIGH_BITS_EXTRACTED]]) diff --git a/llvm/test/Transforms/InstCombine/div-shift.ll b/llvm/test/Transforms/InstCombine/div-shift.ll index 33da4be..b35d8bd 100644 --- a/llvm/test/Transforms/InstCombine/div-shift.ll +++ b/llvm/test/Transforms/InstCombine/div-shift.ll @@ -130,7 +130,7 @@ define i8 @udiv_umax(i8 %x, i8 %y, i8 %z) { ; Negative test, cannot take exact log2 define i8 @udiv_umin_(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @udiv_umin_( -; CHECK-NEXT: [[Y2:%.*]] = shl i8 1, [[Y:%.*]] +; CHECK-NEXT: [[Y2:%.*]] = shl nuw i8 1, [[Y:%.*]] ; CHECK-NEXT: [[M:%.*]] = call i8 @llvm.umin.i8(i8 [[Y2]], i8 [[Z:%.*]]) ; CHECK-NEXT: [[D:%.*]] = udiv i8 [[X:%.*]], [[M]] ; CHECK-NEXT: ret i8 [[D]] @@ -144,8 +144,8 @@ define i8 @udiv_umin_(i8 %x, i8 %y, i8 %z) { ; Negative test, extra use define i8 @udiv_umin_extra_use(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @udiv_umin_extra_use( -; CHECK-NEXT: [[Y2:%.*]] = shl i8 1, [[Y:%.*]] -; CHECK-NEXT: [[Z2:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Y2:%.*]] = shl nuw i8 1, [[Y:%.*]] +; CHECK-NEXT: [[Z2:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[M:%.*]] = call i8 @llvm.umin.i8(i8 [[Y2]], i8 [[Z2]]) ; CHECK-NEXT: call void @use(i8 [[M]]) ; CHECK-NEXT: [[D:%.*]] = udiv i8 [[X:%.*]], [[M]] @@ -162,8 +162,8 @@ define i8 @udiv_umin_extra_use(i8 %x, i8 %y, i8 %z) { ; Negative test, signed min/max define i8 @udiv_smin(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @udiv_smin( -; CHECK-NEXT: [[Y2:%.*]] = shl i8 1, [[Y:%.*]] -; CHECK-NEXT: [[Z2:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Y2:%.*]] = shl nuw i8 1, [[Y:%.*]] +; CHECK-NEXT: [[Z2:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[M:%.*]] = call i8 @llvm.smin.i8(i8 [[Y2]], i8 [[Z2]]) ; CHECK-NEXT: [[D:%.*]] = udiv i8 [[X:%.*]], [[M]] ; CHECK-NEXT: ret i8 [[D]] @@ -178,8 +178,8 @@ define i8 @udiv_smin(i8 %x, i8 %y, i8 %z) { ; Negative test, signed min/max define i8 @udiv_smax(i8 %x, i8 %y, i8 %z) { ; CHECK-LABEL: @udiv_smax( -; CHECK-NEXT: [[Y2:%.*]] = shl i8 1, [[Y:%.*]] -; CHECK-NEXT: [[Z2:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[Y2:%.*]] = shl nuw i8 1, [[Y:%.*]] +; CHECK-NEXT: [[Z2:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: [[M:%.*]] = call i8 @llvm.smax.i8(i8 [[Y2]], i8 [[Z2]]) ; CHECK-NEXT: [[D:%.*]] = udiv i8 [[X:%.*]], [[M]] ; CHECK-NEXT: ret i8 [[D]] @@ -226,7 +226,7 @@ define <2 x i32> @t9(<2 x i32> %x) { define i32 @t10(i32 %x, i32 %y) { ; CHECK-LABEL: @t10( -; CHECK-NEXT: [[R:%.*]] = shl nsw i32 1, [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = shl nuw nsw i32 1, [[Y:%.*]] ; CHECK-NEXT: ret i32 [[R]] ; %shl = shl nsw i32 %x, %y @@ -236,7 +236,7 @@ define i32 @t10(i32 %x, i32 %y) { define <2 x i32> @t11(<2 x i32> %x, <2 x i32> %y) { ; CHECK-LABEL: @t11( -; CHECK-NEXT: [[R:%.*]] = shl nsw <2 x i32> , [[Y:%.*]] +; CHECK-NEXT: [[R:%.*]] = shl nuw nsw <2 x i32> , [[Y:%.*]] ; CHECK-NEXT: ret <2 x i32> [[R]] ; %shl = shl nsw <2 x i32> %x, %y diff --git a/llvm/test/Transforms/InstCombine/get-lowbitmask-upto-and-including-bit.ll b/llvm/test/Transforms/InstCombine/get-lowbitmask-upto-and-including-bit.ll index dc26004..12a81f0 100644 --- a/llvm/test/Transforms/InstCombine/get-lowbitmask-upto-and-including-bit.ll +++ b/llvm/test/Transforms/InstCombine/get-lowbitmask-upto-and-including-bit.ll @@ -78,7 +78,7 @@ define <3 x i8> @t5_vec_undef2(<3 x i8> %x) { ; One-use tests define i8 @t6_extrause0(i8 %x) { ; CHECK-LABEL: @t6_extrause0( -; CHECK-NEXT: [[BITMASK:%.*]] = shl i8 1, [[X:%.*]] +; CHECK-NEXT: [[BITMASK:%.*]] = shl nuw i8 1, [[X:%.*]] ; CHECK-NEXT: call void @use8(i8 [[BITMASK]]) ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 7, [[X]] ; CHECK-NEXT: [[MASK:%.*]] = lshr i8 -1, [[TMP1]] @@ -92,7 +92,7 @@ define i8 @t6_extrause0(i8 %x) { } define i8 @t7_extrause1(i8 %x) { ; CHECK-LABEL: @t7_extrause1( -; CHECK-NEXT: [[BITMASK:%.*]] = shl i8 1, [[X:%.*]] +; CHECK-NEXT: [[BITMASK:%.*]] = shl nuw i8 1, [[X:%.*]] ; CHECK-NEXT: [[LOWBITMASK:%.*]] = add i8 [[BITMASK]], -1 ; CHECK-NEXT: call void @use8(i8 [[LOWBITMASK]]) ; CHECK-NEXT: [[MASK:%.*]] = or i8 [[LOWBITMASK]], [[BITMASK]] @@ -106,7 +106,7 @@ define i8 @t7_extrause1(i8 %x) { } define i8 @t8_extrause2(i8 %x) { ; CHECK-LABEL: @t8_extrause2( -; CHECK-NEXT: [[BITMASK:%.*]] = shl i8 1, [[X:%.*]] +; CHECK-NEXT: [[BITMASK:%.*]] = shl nuw i8 1, [[X:%.*]] ; CHECK-NEXT: call void @use8(i8 [[BITMASK]]) ; CHECK-NEXT: [[LOWBITMASK:%.*]] = add i8 [[BITMASK]], -1 ; CHECK-NEXT: call void @use8(i8 [[LOWBITMASK]]) @@ -124,7 +124,7 @@ define i8 @t8_extrause2(i8 %x) { ; Non-CSE'd test define i8 @t9_nocse(i8 %x) { ; CHECK-LABEL: @t9_nocse( -; CHECK-NEXT: [[BITMASK1:%.*]] = shl i8 1, [[X:%.*]] +; CHECK-NEXT: [[BITMASK1:%.*]] = shl nuw i8 1, [[X:%.*]] ; CHECK-NEXT: [[NOTMASK:%.*]] = shl nsw i8 -1, [[X]] ; CHECK-NEXT: [[LOWBITMASK:%.*]] = xor i8 [[NOTMASK]], -1 ; CHECK-NEXT: [[MASK:%.*]] = or i8 [[BITMASK1]], [[LOWBITMASK]] @@ -140,7 +140,7 @@ define i8 @t9_nocse(i8 %x) { ; Non-CSE'd extra uses test define i8 @t10_nocse_extrause0(i8 %x) { ; CHECK-LABEL: @t10_nocse_extrause0( -; CHECK-NEXT: [[BITMASK0:%.*]] = shl i8 1, [[X:%.*]] +; CHECK-NEXT: [[BITMASK0:%.*]] = shl nuw i8 1, [[X:%.*]] ; CHECK-NEXT: call void @use8(i8 [[BITMASK0]]) ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 7, [[X]] ; CHECK-NEXT: [[MASK:%.*]] = lshr i8 -1, [[TMP1]] @@ -155,7 +155,7 @@ define i8 @t10_nocse_extrause0(i8 %x) { } define i8 @t11_nocse_extrause1(i8 %x) { ; CHECK-LABEL: @t11_nocse_extrause1( -; CHECK-NEXT: [[BITMASK1:%.*]] = shl i8 1, [[X:%.*]] +; CHECK-NEXT: [[BITMASK1:%.*]] = shl nuw i8 1, [[X:%.*]] ; CHECK-NEXT: call void @use8(i8 [[BITMASK1]]) ; CHECK-NEXT: [[NOTMASK:%.*]] = shl nsw i8 -1, [[X]] ; CHECK-NEXT: [[LOWBITMASK:%.*]] = xor i8 [[NOTMASK]], -1 @@ -171,7 +171,7 @@ define i8 @t11_nocse_extrause1(i8 %x) { } define i8 @t12_nocse_extrause2(i8 %x) { ; CHECK-LABEL: @t12_nocse_extrause2( -; CHECK-NEXT: [[BITMASK1:%.*]] = shl i8 1, [[X:%.*]] +; CHECK-NEXT: [[BITMASK1:%.*]] = shl nuw i8 1, [[X:%.*]] ; CHECK-NEXT: [[NOTMASK:%.*]] = shl nsw i8 -1, [[X]] ; CHECK-NEXT: [[LOWBITMASK:%.*]] = xor i8 [[NOTMASK]], -1 ; CHECK-NEXT: call void @use8(i8 [[LOWBITMASK]]) @@ -187,9 +187,9 @@ define i8 @t12_nocse_extrause2(i8 %x) { } define i8 @t13_nocse_extrause3(i8 %x) { ; CHECK-LABEL: @t13_nocse_extrause3( -; CHECK-NEXT: [[BITMASK0:%.*]] = shl i8 1, [[X:%.*]] +; CHECK-NEXT: [[BITMASK0:%.*]] = shl nuw i8 1, [[X:%.*]] ; CHECK-NEXT: call void @use8(i8 [[BITMASK0]]) -; CHECK-NEXT: [[BITMASK1:%.*]] = shl i8 1, [[X]] +; CHECK-NEXT: [[BITMASK1:%.*]] = shl nuw i8 1, [[X]] ; CHECK-NEXT: call void @use8(i8 [[BITMASK1]]) ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 7, [[X]] ; CHECK-NEXT: [[MASK:%.*]] = lshr i8 -1, [[TMP1]] @@ -205,7 +205,7 @@ define i8 @t13_nocse_extrause3(i8 %x) { } define i8 @t14_nocse_extrause4(i8 %x) { ; CHECK-LABEL: @t14_nocse_extrause4( -; CHECK-NEXT: [[BITMASK0:%.*]] = shl i8 1, [[X:%.*]] +; CHECK-NEXT: [[BITMASK0:%.*]] = shl nuw i8 1, [[X:%.*]] ; CHECK-NEXT: call void @use8(i8 [[BITMASK0]]) ; CHECK-NEXT: [[LOWBITMASK:%.*]] = add i8 [[BITMASK0]], -1 ; CHECK-NEXT: call void @use8(i8 [[LOWBITMASK]]) @@ -223,7 +223,7 @@ define i8 @t14_nocse_extrause4(i8 %x) { } define i8 @t15_nocse_extrause5(i8 %x) { ; CHECK-LABEL: @t15_nocse_extrause5( -; CHECK-NEXT: [[BITMASK1:%.*]] = shl i8 1, [[X:%.*]] +; CHECK-NEXT: [[BITMASK1:%.*]] = shl nuw i8 1, [[X:%.*]] ; CHECK-NEXT: call void @use8(i8 [[BITMASK1]]) ; CHECK-NEXT: [[NOTMASK:%.*]] = shl nsw i8 -1, [[X]] ; CHECK-NEXT: [[LOWBITMASK:%.*]] = xor i8 [[NOTMASK]], -1 @@ -241,9 +241,9 @@ define i8 @t15_nocse_extrause5(i8 %x) { } define i8 @t16_nocse_extrause6(i8 %x) { ; CHECK-LABEL: @t16_nocse_extrause6( -; CHECK-NEXT: [[BITMASK0:%.*]] = shl i8 1, [[X:%.*]] +; CHECK-NEXT: [[BITMASK0:%.*]] = shl nuw i8 1, [[X:%.*]] ; CHECK-NEXT: call void @use8(i8 [[BITMASK0]]) -; CHECK-NEXT: [[BITMASK1:%.*]] = shl i8 1, [[X]] +; CHECK-NEXT: [[BITMASK1:%.*]] = shl nuw i8 1, [[X]] ; CHECK-NEXT: call void @use8(i8 [[BITMASK1]]) ; CHECK-NEXT: [[LOWBITMASK:%.*]] = add i8 [[BITMASK0]], -1 ; CHECK-NEXT: call void @use8(i8 [[LOWBITMASK]]) @@ -263,7 +263,7 @@ define i8 @t16_nocse_extrause6(i8 %x) { ; Non-CSE'd test with mismatching X's. define i8 @t17_nocse_mismatching_x(i8 %x0, i8 %x1) { ; CHECK-LABEL: @t17_nocse_mismatching_x( -; CHECK-NEXT: [[BITMASK1:%.*]] = shl i8 1, [[X1:%.*]] +; CHECK-NEXT: [[BITMASK1:%.*]] = shl nuw i8 1, [[X1:%.*]] ; CHECK-NEXT: [[NOTMASK:%.*]] = shl nsw i8 -1, [[X0:%.*]] ; CHECK-NEXT: [[LOWBITMASK:%.*]] = xor i8 [[NOTMASK]], -1 ; CHECK-NEXT: [[MASK:%.*]] = or i8 [[BITMASK1]], [[LOWBITMASK]] diff --git a/llvm/test/Transforms/InstCombine/icmp-trunc.ll b/llvm/test/Transforms/InstCombine/icmp-trunc.ll index 1a3ffdd..b2de9dd 100644 --- a/llvm/test/Transforms/InstCombine/icmp-trunc.ll +++ b/llvm/test/Transforms/InstCombine/icmp-trunc.ll @@ -379,7 +379,7 @@ define <2 x i1> @shl1_trunc_ne0(<2 x i8> %a) { define i1 @shl1_trunc_eq0_use1(i8 %a) { ; CHECK-LABEL: @shl1_trunc_eq0_use1( -; CHECK-NEXT: [[SHL:%.*]] = shl i8 1, [[A:%.*]] +; CHECK-NEXT: [[SHL:%.*]] = shl nuw i8 1, [[A:%.*]] ; CHECK-NEXT: call void @use(i8 [[SHL]]) ; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[A]], 5 ; CHECK-NEXT: ret i1 [[R]] @@ -393,7 +393,7 @@ define i1 @shl1_trunc_eq0_use1(i8 %a) { define i1 @shl1_trunc_ne0_use2(i37 %a) { ; CHECK-LABEL: @shl1_trunc_ne0_use2( -; CHECK-NEXT: [[SHL:%.*]] = shl i37 1, [[A:%.*]] +; CHECK-NEXT: [[SHL:%.*]] = shl nuw i37 1, [[A:%.*]] ; CHECK-NEXT: [[T:%.*]] = trunc i37 [[SHL]] to i8 ; CHECK-NEXT: call void @use(i8 [[T]]) ; CHECK-NEXT: [[R:%.*]] = icmp ult i37 [[A]], 8 @@ -465,7 +465,7 @@ define <2 x i1> @shl4_trunc_ne0(<2 x i8> %a) { define i1 @shl1_trunc_sgt0(i9 %a) { ; CHECK-LABEL: @shl1_trunc_sgt0( -; CHECK-NEXT: [[SHL:%.*]] = shl i9 1, [[A:%.*]] +; CHECK-NEXT: [[SHL:%.*]] = shl nuw i9 1, [[A:%.*]] ; CHECK-NEXT: [[T:%.*]] = trunc i9 [[SHL]] to i6 ; CHECK-NEXT: [[R:%.*]] = icmp sgt i6 [[T]], 0 ; CHECK-NEXT: ret i1 [[R]] @@ -478,7 +478,7 @@ define i1 @shl1_trunc_sgt0(i9 %a) { define i1 @shl1_trunc_eq1(i64 %a) { ; CHECK-LABEL: @shl1_trunc_eq1( -; CHECK-NEXT: [[SHL:%.*]] = shl i64 1, [[A:%.*]] +; CHECK-NEXT: [[SHL:%.*]] = shl nuw i64 1, [[A:%.*]] ; CHECK-NEXT: [[T:%.*]] = trunc i64 [[SHL]] to i8 ; CHECK-NEXT: call void @use(i8 [[T]]) ; CHECK-NEXT: [[R:%.*]] = icmp eq i64 [[A]], 0 @@ -493,7 +493,7 @@ define i1 @shl1_trunc_eq1(i64 %a) { define i1 @shl1_trunc_ne32(i8 %a) { ; CHECK-LABEL: @shl1_trunc_ne32( -; CHECK-NEXT: [[SHL:%.*]] = shl i8 1, [[A:%.*]] +; CHECK-NEXT: [[SHL:%.*]] = shl nuw i8 1, [[A:%.*]] ; CHECK-NEXT: call void @use(i8 [[SHL]]) ; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[A]], 5 ; CHECK-NEXT: ret i1 [[R]] @@ -545,7 +545,7 @@ define i1 @shl2_trunc_ne8_i32(i32 %a) { define i1 @shl1_trunc_sgt4(i32 %a) { ; CHECK-LABEL: @shl1_trunc_sgt4( -; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, [[A:%.*]] +; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, [[A:%.*]] ; CHECK-NEXT: [[T:%.*]] = trunc i32 [[SHL]] to i16 ; CHECK-NEXT: [[R:%.*]] = icmp sgt i16 [[T]], 4 ; CHECK-NEXT: ret i1 [[R]] diff --git a/llvm/test/Transforms/InstCombine/icmp-uge-of-add-of-shl-one-by-bits-to-allones-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll b/llvm/test/Transforms/InstCombine/icmp-uge-of-add-of-shl-one-by-bits-to-allones-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll index 4e11376..b694ac0 100644 --- a/llvm/test/Transforms/InstCombine/icmp-uge-of-add-of-shl-one-by-bits-to-allones-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll +++ b/llvm/test/Transforms/InstCombine/icmp-uge-of-add-of-shl-one-by-bits-to-allones-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll @@ -20,7 +20,7 @@ declare void @use3i8(<3 x i8>) define i1 @p0(i8 %val, i8 %bits) { ; CHECK-LABEL: @p0( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[BITS:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[VAL_HIGHBITS:%.*]] = lshr i8 [[VAL:%.*]], [[BITS]] ; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[VAL_HIGHBITS]], 0 @@ -39,7 +39,7 @@ define i1 @p0(i8 %val, i8 %bits) { define <2 x i1> @p1_vec(<2 x i8> %val, <2 x i8> %bits) { ; CHECK-LABEL: @p1_vec( -; CHECK-NEXT: [[T0:%.*]] = shl <2 x i8> , [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw <2 x i8> , [[BITS:%.*]] ; CHECK-NEXT: call void @use2i8(<2 x i8> [[T0]]) ; CHECK-NEXT: [[VAL_HIGHBITS:%.*]] = lshr <2 x i8> [[VAL:%.*]], [[BITS]] ; CHECK-NEXT: [[R:%.*]] = icmp eq <2 x i8> [[VAL_HIGHBITS]], zeroinitializer @@ -54,7 +54,7 @@ define <2 x i1> @p1_vec(<2 x i8> %val, <2 x i8> %bits) { define <3 x i1> @p2_vec_undef0(<3 x i8> %val, <3 x i8> %bits) { ; CHECK-LABEL: @p2_vec_undef0( -; CHECK-NEXT: [[T0:%.*]] = shl <3 x i8> , [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> , [[BITS:%.*]] ; CHECK-NEXT: call void @use3i8(<3 x i8> [[T0]]) ; CHECK-NEXT: [[VAL_HIGHBITS:%.*]] = lshr <3 x i8> [[VAL:%.*]], [[BITS]] ; CHECK-NEXT: [[R:%.*]] = icmp eq <3 x i8> [[VAL_HIGHBITS]], zeroinitializer @@ -69,7 +69,7 @@ define <3 x i1> @p2_vec_undef0(<3 x i8> %val, <3 x i8> %bits) { define <3 x i1> @p2_vec_undef1(<3 x i8> %val, <3 x i8> %bits) { ; CHECK-LABEL: @p2_vec_undef1( -; CHECK-NEXT: [[T0:%.*]] = shl <3 x i8> , [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> , [[BITS:%.*]] ; CHECK-NEXT: call void @use3i8(<3 x i8> [[T0]]) ; CHECK-NEXT: [[VAL_HIGHBITS:%.*]] = lshr <3 x i8> [[VAL:%.*]], [[BITS]] ; CHECK-NEXT: [[R:%.*]] = icmp eq <3 x i8> [[VAL_HIGHBITS]], zeroinitializer @@ -84,7 +84,7 @@ define <3 x i1> @p2_vec_undef1(<3 x i8> %val, <3 x i8> %bits) { define <3 x i1> @p2_vec_undef2(<3 x i8> %val, <3 x i8> %bits) { ; CHECK-LABEL: @p2_vec_undef2( -; CHECK-NEXT: [[T0:%.*]] = shl <3 x i8> , [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> , [[BITS:%.*]] ; CHECK-NEXT: call void @use3i8(<3 x i8> [[T0]]) ; CHECK-NEXT: [[VAL_HIGHBITS:%.*]] = lshr <3 x i8> [[VAL:%.*]], [[BITS]] ; CHECK-NEXT: [[R:%.*]] = icmp eq <3 x i8> [[VAL_HIGHBITS]], zeroinitializer @@ -105,7 +105,7 @@ declare i8 @gen8() define i1 @c0(i8 %bits) { ; CHECK-LABEL: @c0( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[BITS:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[VAL:%.*]] = call i8 @gen8() ; CHECK-NEXT: [[VAL_HIGHBITS:%.*]] = lshr i8 [[VAL]], [[BITS]] @@ -123,9 +123,9 @@ define i1 @c0(i8 %bits) { ; What if we have the same pattern on both sides? define i1 @both(i8 %bits0, i8 %bits1) { ; CHECK-LABEL: @both( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[BITS0:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[BITS0:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) -; CHECK-NEXT: [[T2:%.*]] = shl i8 1, [[BITS1:%.*]] +; CHECK-NEXT: [[T2:%.*]] = shl nuw i8 1, [[BITS1:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T2]]) ; CHECK-NEXT: [[T3:%.*]] = add i8 [[T2]], -1 ; CHECK-NEXT: [[T3_HIGHBITS:%.*]] = lshr i8 [[T3]], [[BITS0]] @@ -148,7 +148,7 @@ define i1 @both(i8 %bits0, i8 %bits1) { define i1 @oneuse(i8 %val, i8 %bits) { ; CHECK-LABEL: @oneuse( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[BITS:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0]], -1 ; CHECK-NEXT: call void @use8(i8 [[T1]]) @@ -184,9 +184,9 @@ define i1 @n0(i8 %val, i8 %bits) { define i1 @n1(i8 %val, i8 %bits) { ; CHECK-LABEL: @n1( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[BITS:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) -; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0]], 1 +; CHECK-NEXT: [[T1:%.*]] = add nuw i8 [[T0]], 1 ; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[T1]], [[VAL:%.*]] ; CHECK-NEXT: ret i1 [[R]] ; @@ -214,7 +214,7 @@ define <2 x i1> @n2_vec_nonsplat(<2 x i8> %val, <2 x i8> %bits) { define <2 x i1> @n3_vec_nonsplat(<2 x i8> %val, <2 x i8> %bits) { ; CHECK-LABEL: @n3_vec_nonsplat( -; CHECK-NEXT: [[T0:%.*]] = shl <2 x i8> , [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw <2 x i8> , [[BITS:%.*]] ; CHECK-NEXT: call void @use2i8(<2 x i8> [[T0]]) ; CHECK-NEXT: [[T1:%.*]] = add <2 x i8> [[T0]], ; CHECK-NEXT: [[R:%.*]] = icmp uge <2 x i8> [[T1]], [[VAL:%.*]] @@ -229,7 +229,7 @@ define <2 x i1> @n3_vec_nonsplat(<2 x i8> %val, <2 x i8> %bits) { define i1 @n3(i8 %val, i8 %bits) { ; CHECK-LABEL: @n3( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[BITS:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0]], -1 ; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[T1]], [[VAL:%.*]] @@ -244,7 +244,7 @@ define i1 @n3(i8 %val, i8 %bits) { define i1 @n4(i8 %bits) { ; CHECK-LABEL: @n4( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[BITS:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0]], -1 ; CHECK-NEXT: [[VAL:%.*]] = call i8 @gen8() diff --git a/llvm/test/Transforms/InstCombine/icmp-uge-of-not-of-shl-allones-by-bits-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll b/llvm/test/Transforms/InstCombine/icmp-uge-of-not-of-shl-allones-by-bits-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll index 36de1d1..001a547 100644 --- a/llvm/test/Transforms/InstCombine/icmp-uge-of-not-of-shl-allones-by-bits-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll +++ b/llvm/test/Transforms/InstCombine/icmp-uge-of-not-of-shl-allones-by-bits-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll @@ -171,7 +171,7 @@ define i1 @oneuse2(i8 %val, i8 %bits) { define i1 @n0(i8 %val, i8 %bits) { ; CHECK-LABEL: @n0( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[BITS:%.*]] ; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 ; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[T1]], [[VAL:%.*]] ; CHECK-NEXT: ret i1 [[R]] diff --git a/llvm/test/Transforms/InstCombine/icmp-ugt-of-shl-1-by-bits-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll b/llvm/test/Transforms/InstCombine/icmp-ugt-of-shl-1-by-bits-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll index 8d8022d..550e8bb 100644 --- a/llvm/test/Transforms/InstCombine/icmp-ugt-of-shl-1-by-bits-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll +++ b/llvm/test/Transforms/InstCombine/icmp-ugt-of-shl-1-by-bits-and-val-to-icmp-eq-of-lshr-val-by-bits-and-0.ll @@ -71,7 +71,7 @@ define i1 @c0(i8 %bits) { ; What if we have the same pattern on both sides? define i1 @both(i8 %bits0, i8 %bits1) { ; CHECK-LABEL: @both( -; CHECK-NEXT: [[T1:%.*]] = shl i8 1, [[BITS1:%.*]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw i8 1, [[BITS1:%.*]] ; CHECK-NEXT: [[T1_HIGHBITS:%.*]] = lshr i8 [[T1]], [[BITS0:%.*]] ; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[T1_HIGHBITS]], 0 ; CHECK-NEXT: ret i1 [[R]] @@ -90,7 +90,7 @@ declare void @use8(i8) define i1 @oneuse0(i8 %val, i8 %bits) { ; CHECK-LABEL: @oneuse0( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[BITS:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[T0]], [[VAL:%.*]] ; CHECK-NEXT: ret i1 [[R]] @@ -129,7 +129,7 @@ define <2 x i1> @n1_vec_nonsplat(<2 x i8> %val, <2 x i8> %bits) { define i1 @n2(i8 %val, i8 %bits) { ; CHECK-LABEL: @n2( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[BITS:%.*]] ; CHECK-NEXT: [[R:%.*]] = icmp uge i8 [[T0]], [[VAL:%.*]] ; CHECK-NEXT: ret i1 [[R]] ; @@ -140,7 +140,7 @@ define i1 @n2(i8 %val, i8 %bits) { define i1 @n3(i8 %bits) { ; CHECK-LABEL: @n3( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[BITS:%.*]] ; CHECK-NEXT: [[VAL:%.*]] = call i8 @gen8() ; CHECK-NEXT: [[R:%.*]] = icmp ule i8 [[VAL]], [[T0]] ; CHECK-NEXT: ret i1 [[R]] diff --git a/llvm/test/Transforms/InstCombine/icmp-ule-of-shl-1-by-bits-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll b/llvm/test/Transforms/InstCombine/icmp-ule-of-shl-1-by-bits-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll index 7f47ae7..26b667d 100644 --- a/llvm/test/Transforms/InstCombine/icmp-ule-of-shl-1-by-bits-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll +++ b/llvm/test/Transforms/InstCombine/icmp-ule-of-shl-1-by-bits-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll @@ -71,7 +71,7 @@ define i1 @c0(i8 %bits) { ; What if we have the same pattern on both sides? define i1 @both(i8 %bits0, i8 %bits1) { ; CHECK-LABEL: @both( -; CHECK-NEXT: [[T1:%.*]] = shl i8 1, [[BITS1:%.*]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw i8 1, [[BITS1:%.*]] ; CHECK-NEXT: [[T1_HIGHBITS:%.*]] = lshr i8 [[T1]], [[BITS0:%.*]] ; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[T1_HIGHBITS]], 0 ; CHECK-NEXT: ret i1 [[R]] @@ -90,7 +90,7 @@ declare void @use8(i8) define i1 @oneuse0(i8 %val, i8 %bits) { ; CHECK-LABEL: @oneuse0( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[BITS:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[R:%.*]] = icmp ule i8 [[T0]], [[VAL:%.*]] ; CHECK-NEXT: ret i1 [[R]] @@ -129,7 +129,7 @@ define <2 x i1> @n1_vec_nonsplat(<2 x i8> %val, <2 x i8> %bits) { define i1 @n2(i8 %val, i8 %bits) { ; CHECK-LABEL: @n2( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[BITS:%.*]] ; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[T0]], [[VAL:%.*]] ; CHECK-NEXT: ret i1 [[R]] ; @@ -140,7 +140,7 @@ define i1 @n2(i8 %val, i8 %bits) { define i1 @n3(i8 %bits) { ; CHECK-LABEL: @n3( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[BITS:%.*]] ; CHECK-NEXT: [[VAL:%.*]] = call i8 @gen8() ; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[VAL]], [[T0]] ; CHECK-NEXT: ret i1 [[R]] diff --git a/llvm/test/Transforms/InstCombine/icmp-ult-of-add-of-shl-one-by-bits-to-allones-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll b/llvm/test/Transforms/InstCombine/icmp-ult-of-add-of-shl-one-by-bits-to-allones-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll index 94b2b507f..f9a4c9d 100644 --- a/llvm/test/Transforms/InstCombine/icmp-ult-of-add-of-shl-one-by-bits-to-allones-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll +++ b/llvm/test/Transforms/InstCombine/icmp-ult-of-add-of-shl-one-by-bits-to-allones-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll @@ -20,7 +20,7 @@ declare void @use3i8(<3 x i8>) define i1 @p0(i8 %val, i8 %bits) { ; CHECK-LABEL: @p0( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[BITS:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[VAL_HIGHBITS:%.*]] = lshr i8 [[VAL:%.*]], [[BITS]] ; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[VAL_HIGHBITS]], 0 @@ -39,7 +39,7 @@ define i1 @p0(i8 %val, i8 %bits) { define <2 x i1> @p1_vec(<2 x i8> %val, <2 x i8> %bits) { ; CHECK-LABEL: @p1_vec( -; CHECK-NEXT: [[T0:%.*]] = shl <2 x i8> , [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw <2 x i8> , [[BITS:%.*]] ; CHECK-NEXT: call void @use2i8(<2 x i8> [[T0]]) ; CHECK-NEXT: [[VAL_HIGHBITS:%.*]] = lshr <2 x i8> [[VAL:%.*]], [[BITS]] ; CHECK-NEXT: [[R:%.*]] = icmp ne <2 x i8> [[VAL_HIGHBITS]], zeroinitializer @@ -54,7 +54,7 @@ define <2 x i1> @p1_vec(<2 x i8> %val, <2 x i8> %bits) { define <3 x i1> @p2_vec_undef0(<3 x i8> %val, <3 x i8> %bits) { ; CHECK-LABEL: @p2_vec_undef0( -; CHECK-NEXT: [[T0:%.*]] = shl <3 x i8> , [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> , [[BITS:%.*]] ; CHECK-NEXT: call void @use3i8(<3 x i8> [[T0]]) ; CHECK-NEXT: [[VAL_HIGHBITS:%.*]] = lshr <3 x i8> [[VAL:%.*]], [[BITS]] ; CHECK-NEXT: [[R:%.*]] = icmp ne <3 x i8> [[VAL_HIGHBITS]], zeroinitializer @@ -69,7 +69,7 @@ define <3 x i1> @p2_vec_undef0(<3 x i8> %val, <3 x i8> %bits) { define <3 x i1> @p2_vec_undef1(<3 x i8> %val, <3 x i8> %bits) { ; CHECK-LABEL: @p2_vec_undef1( -; CHECK-NEXT: [[T0:%.*]] = shl <3 x i8> , [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> , [[BITS:%.*]] ; CHECK-NEXT: call void @use3i8(<3 x i8> [[T0]]) ; CHECK-NEXT: [[VAL_HIGHBITS:%.*]] = lshr <3 x i8> [[VAL:%.*]], [[BITS]] ; CHECK-NEXT: [[R:%.*]] = icmp ne <3 x i8> [[VAL_HIGHBITS]], zeroinitializer @@ -84,7 +84,7 @@ define <3 x i1> @p2_vec_undef1(<3 x i8> %val, <3 x i8> %bits) { define <3 x i1> @p2_vec_undef2(<3 x i8> %val, <3 x i8> %bits) { ; CHECK-LABEL: @p2_vec_undef2( -; CHECK-NEXT: [[T0:%.*]] = shl <3 x i8> , [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw <3 x i8> , [[BITS:%.*]] ; CHECK-NEXT: call void @use3i8(<3 x i8> [[T0]]) ; CHECK-NEXT: [[VAL_HIGHBITS:%.*]] = lshr <3 x i8> [[VAL:%.*]], [[BITS]] ; CHECK-NEXT: [[R:%.*]] = icmp ne <3 x i8> [[VAL_HIGHBITS]], zeroinitializer @@ -105,7 +105,7 @@ declare i8 @gen8() define i1 @c0(i8 %bits) { ; CHECK-LABEL: @c0( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[BITS:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[VAL:%.*]] = call i8 @gen8() ; CHECK-NEXT: [[VAL_HIGHBITS:%.*]] = lshr i8 [[VAL]], [[BITS]] @@ -123,9 +123,9 @@ define i1 @c0(i8 %bits) { ; What if we have the same pattern on both sides? define i1 @both(i8 %bits0, i8 %bits1) { ; CHECK-LABEL: @both( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[BITS0:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[BITS0:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) -; CHECK-NEXT: [[T2:%.*]] = shl i8 1, [[BITS1:%.*]] +; CHECK-NEXT: [[T2:%.*]] = shl nuw i8 1, [[BITS1:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T2]]) ; CHECK-NEXT: [[T3:%.*]] = add i8 [[T2]], -1 ; CHECK-NEXT: [[T3_HIGHBITS:%.*]] = lshr i8 [[T3]], [[BITS0]] @@ -148,7 +148,7 @@ define i1 @both(i8 %bits0, i8 %bits1) { define i1 @oneuse(i8 %val, i8 %bits) { ; CHECK-LABEL: @oneuse( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[BITS:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0]], -1 ; CHECK-NEXT: call void @use8(i8 [[T1]]) @@ -184,9 +184,9 @@ define i1 @n0(i8 %val, i8 %bits) { define i1 @n1(i8 %val, i8 %bits) { ; CHECK-LABEL: @n1( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[BITS:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) -; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0]], 1 +; CHECK-NEXT: [[T1:%.*]] = add nuw i8 [[T0]], 1 ; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[T1]], [[VAL:%.*]] ; CHECK-NEXT: ret i1 [[R]] ; @@ -214,7 +214,7 @@ define <2 x i1> @n2_vec_nonsplat(<2 x i8> %val, <2 x i8> %bits) { define <2 x i1> @n3_vec_nonsplat(<2 x i8> %val, <2 x i8> %bits) { ; CHECK-LABEL: @n3_vec_nonsplat( -; CHECK-NEXT: [[T0:%.*]] = shl <2 x i8> , [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw <2 x i8> , [[BITS:%.*]] ; CHECK-NEXT: call void @use2i8(<2 x i8> [[T0]]) ; CHECK-NEXT: [[T1:%.*]] = add <2 x i8> [[T0]], ; CHECK-NEXT: [[R:%.*]] = icmp ult <2 x i8> [[T1]], [[VAL:%.*]] @@ -229,7 +229,7 @@ define <2 x i1> @n3_vec_nonsplat(<2 x i8> %val, <2 x i8> %bits) { define i1 @n3(i8 %val, i8 %bits) { ; CHECK-LABEL: @n3( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[BITS:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0]], -1 ; CHECK-NEXT: [[R:%.*]] = icmp ule i8 [[T1]], [[VAL:%.*]] @@ -244,7 +244,7 @@ define i1 @n3(i8 %val, i8 %bits) { define i1 @n4(i8 %bits) { ; CHECK-LABEL: @n4( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[BITS:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[T1:%.*]] = add i8 [[T0]], -1 ; CHECK-NEXT: [[VAL:%.*]] = call i8 @gen8() diff --git a/llvm/test/Transforms/InstCombine/icmp-ult-of-not-of-shl-allones-by-bits-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll b/llvm/test/Transforms/InstCombine/icmp-ult-of-not-of-shl-allones-by-bits-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll index a6e6b1c..d8d9768 100644 --- a/llvm/test/Transforms/InstCombine/icmp-ult-of-not-of-shl-allones-by-bits-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll +++ b/llvm/test/Transforms/InstCombine/icmp-ult-of-not-of-shl-allones-by-bits-and-val-to-icmp-ne-of-lshr-val-by-bits-and-0.ll @@ -171,7 +171,7 @@ define i1 @oneuse2(i8 %val, i8 %bits) { define i1 @n0(i8 %val, i8 %bits) { ; CHECK-LABEL: @n0( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[BITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[BITS:%.*]] ; CHECK-NEXT: [[T1:%.*]] = xor i8 [[T0]], -1 ; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[T1]], [[VAL:%.*]] ; CHECK-NEXT: ret i1 [[R]] diff --git a/llvm/test/Transforms/InstCombine/icmp.ll b/llvm/test/Transforms/InstCombine/icmp.ll index 0041323..8126029 100644 --- a/llvm/test/Transforms/InstCombine/icmp.ll +++ b/llvm/test/Transforms/InstCombine/icmp.ll @@ -1763,7 +1763,7 @@ define <2 x i1> @icmp_sub57_sge_sub20_vec_nonsplat(<2 x i32> %x, <2 x i32> %y) { define i1 @icmp_and_shl_neg_ne_0(i32 %A, i32 %B) { ; CHECK-LABEL: @icmp_and_shl_neg_ne_0( -; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, [[B:%.*]] +; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, [[B:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[SHL]], [[A:%.*]] ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], 0 ; CHECK-NEXT: ret i1 [[CMP]] @@ -1777,7 +1777,7 @@ define i1 @icmp_and_shl_neg_ne_0(i32 %A, i32 %B) { define i1 @icmp_and_shl_neg_eq_0(i32 %A, i32 %B) { ; CHECK-LABEL: @icmp_and_shl_neg_eq_0( -; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, [[B:%.*]] +; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, [[B:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[SHL]], [[A:%.*]] ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP1]], 0 ; CHECK-NEXT: ret i1 [[CMP]] diff --git a/llvm/test/Transforms/InstCombine/memchr.ll b/llvm/test/Transforms/InstCombine/memchr.ll index 569c667..7929d43 100644 --- a/llvm/test/Transforms/InstCombine/memchr.ll +++ b/llvm/test/Transforms/InstCombine/memchr.ll @@ -125,7 +125,7 @@ define i1 @test11(i32 %C) { ; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[C:%.*]] to i16 ; CHECK-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 255 ; CHECK-NEXT: [[MEMCHR_BOUNDS:%.*]] = icmp ult i16 [[TMP2]], 16 -; CHECK-NEXT: [[TMP3:%.*]] = shl i16 1, [[TMP2]] +; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i16 1, [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = and i16 [[TMP3]], 9217 ; CHECK-NEXT: [[MEMCHR_BITS:%.*]] = icmp ne i16 [[TMP4]], 0 ; CHECK-NEXT: [[MEMCHR:%.*]] = select i1 [[MEMCHR_BOUNDS]], i1 [[MEMCHR_BITS]], i1 false diff --git a/llvm/test/Transforms/InstCombine/mul-inseltpoison.ll b/llvm/test/Transforms/InstCombine/mul-inseltpoison.ll index 8ce4540..fe6282f 100644 --- a/llvm/test/Transforms/InstCombine/mul-inseltpoison.ll +++ b/llvm/test/Transforms/InstCombine/mul-inseltpoison.ll @@ -87,8 +87,8 @@ define i32 @test12(i32 %a, i32 %b) { ; rdar://7293527 define i32 @test15(i32 %A, i32 %B) { ; CHECK-LABEL: @test15( -; CHECK-NEXT: [[M:%.*]] = shl i32 [[A:%.*]], [[B:%.*]] -; CHECK-NEXT: ret i32 [[M]] +; CHECK-NEXT: [[M1:%.*]] = shl i32 [[A:%.*]], [[B:%.*]] +; CHECK-NEXT: ret i32 [[M1]] ; %shl = shl i32 1, %B %m = mul i32 %shl, %A @@ -512,8 +512,8 @@ define <3 x i4> @neg_mul_constant_vec_weird(<3 x i4> %a) { define i32 @test26(i32 %A, i32 %B) { ; CHECK-LABEL: @test26( -; CHECK-NEXT: [[D:%.*]] = shl nsw i32 [[A:%.*]], [[B:%.*]] -; CHECK-NEXT: ret i32 [[D]] +; CHECK-NEXT: [[D1:%.*]] = shl nsw i32 [[A:%.*]], [[B:%.*]] +; CHECK-NEXT: ret i32 [[D1]] ; %C = shl nsw i32 1, %B %D = mul nsw i32 %A, %C @@ -522,8 +522,8 @@ define i32 @test26(i32 %A, i32 %B) { define i32 @test27(i32 %A, i32 %B) { ; CHECK-LABEL: @test27( -; CHECK-NEXT: [[D:%.*]] = shl nuw i32 [[A:%.*]], [[B:%.*]] -; CHECK-NEXT: ret i32 [[D]] +; CHECK-NEXT: [[D1:%.*]] = shl nuw i32 [[A:%.*]], [[B:%.*]] +; CHECK-NEXT: ret i32 [[D1]] ; %C = shl i32 1, %B %D = mul nuw i32 %A, %C @@ -532,9 +532,9 @@ define i32 @test27(i32 %A, i32 %B) { define i32 @test28(i32 %A) { ; CHECK-LABEL: @test28( -; CHECK-NEXT: [[B:%.*]] = shl i32 1, [[A:%.*]] -; CHECK-NEXT: [[C:%.*]] = shl i32 [[B]], [[A]] -; CHECK-NEXT: ret i32 [[C]] +; CHECK-NEXT: [[B:%.*]] = shl nuw i32 1, [[A:%.*]] +; CHECK-NEXT: [[C1:%.*]] = shl i32 [[B]], [[A]] +; CHECK-NEXT: ret i32 [[C1]] ; %B = shl i32 1, %A %C = mul nsw i32 %B, %B @@ -570,8 +570,8 @@ define i64 @test30(i32 %A, i32 %B) { @PR22087 = external global i32 define i32 @test31(i32 %V) { ; CHECK-LABEL: @test31( -; CHECK-NEXT: [[MUL:%.*]] = shl i32 [[V:%.*]], zext (i1 icmp ne (ptr inttoptr (i64 1 to ptr), ptr @PR22087) to i32) -; CHECK-NEXT: ret i32 [[MUL]] +; CHECK-NEXT: [[MUL1:%.*]] = shl i32 [[V:%.*]], zext (i1 icmp ne (ptr inttoptr (i64 1 to ptr), ptr @PR22087) to i32) +; CHECK-NEXT: ret i32 [[MUL1]] ; %mul = mul i32 %V, shl (i32 1, i32 zext (i1 icmp ne (ptr inttoptr (i64 1 to ptr), ptr @PR22087) to i32)) ret i32 %mul diff --git a/llvm/test/Transforms/InstCombine/mul.ll b/llvm/test/Transforms/InstCombine/mul.ll index 4cb2468..aefeb99 100644 --- a/llvm/test/Transforms/InstCombine/mul.ll +++ b/llvm/test/Transforms/InstCombine/mul.ll @@ -137,7 +137,7 @@ define i32 @shl1_nuw_commute(i32 %A, i32 %B) { define i32 @shl1_nsw(i32 %A) { ; CHECK-LABEL: @shl1_nsw( -; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, [[A:%.*]] +; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, [[A:%.*]] ; CHECK-NEXT: [[C1:%.*]] = shl i32 [[SHL]], [[A]] ; CHECK-NEXT: ret i32 [[C1]] ; @@ -214,9 +214,9 @@ define i5 @shl1_nsw_nsw_increment_commute(i5 %x, i5 %y) { define i32 @shl1_increment_use(i32 %x, i32 %y) { ; CHECK-LABEL: @shl1_increment_use( -; CHECK-NEXT: [[POW2X:%.*]] = shl i32 1, [[X:%.*]] +; CHECK-NEXT: [[POW2X:%.*]] = shl nuw i32 1, [[X:%.*]] ; CHECK-NEXT: call void @use32(i32 [[POW2X]]) -; CHECK-NEXT: [[X1:%.*]] = add i32 [[POW2X]], 1 +; CHECK-NEXT: [[X1:%.*]] = add nuw i32 [[POW2X]], 1 ; CHECK-NEXT: [[M:%.*]] = mul i32 [[X1]], [[Y:%.*]] ; CHECK-NEXT: ret i32 [[M]] ; diff --git a/llvm/test/Transforms/InstCombine/onehot_merge.ll b/llvm/test/Transforms/InstCombine/onehot_merge.ll index 261e513..73d4600 100644 --- a/llvm/test/Transforms/InstCombine/onehot_merge.ll +++ b/llvm/test/Transforms/InstCombine/onehot_merge.ll @@ -45,8 +45,8 @@ define <2 x i1> @and_consts_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i32> %c2) { define i1 @foo1_and(i32 %k, i32 %c1, i32 %c2) { ; CHECK-LABEL: @foo1_and( -; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]] -; CHECK-NEXT: [[T4:%.*]] = shl i32 1, [[C2:%.*]] +; CHECK-NEXT: [[T:%.*]] = shl nuw i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T4:%.*]] = shl nuw i32 1, [[C2:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]] ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] @@ -64,8 +64,8 @@ define i1 @foo1_and(i32 %k, i32 %c1, i32 %c2) { define i1 @foo1_and_logical(i32 %k, i32 %c1, i32 %c2) { ; CHECK-LABEL: @foo1_and_logical( -; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]] -; CHECK-NEXT: [[T4:%.*]] = shl i32 1, [[C2:%.*]] +; CHECK-NEXT: [[T:%.*]] = shl nuw i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T4:%.*]] = shl nuw i32 1, [[C2:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T4]] ; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T]], [[TMP1]] ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], [[K:%.*]] @@ -84,8 +84,8 @@ define i1 @foo1_and_logical(i32 %k, i32 %c1, i32 %c2) { define <2 x i1> @foo1_and_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i32> %c2) { ; CHECK-LABEL: @foo1_and_vector( -; CHECK-NEXT: [[T:%.*]] = shl <2 x i32> , [[C1:%.*]] -; CHECK-NEXT: [[T4:%.*]] = shl <2 x i32> , [[C2:%.*]] +; CHECK-NEXT: [[T:%.*]] = shl nuw <2 x i32> , [[C1:%.*]] +; CHECK-NEXT: [[T4:%.*]] = shl nuw <2 x i32> , [[C2:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[T]], [[T4]] ; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], [[K:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i32> [[TMP2]], [[TMP1]] @@ -105,8 +105,8 @@ define <2 x i1> @foo1_and_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i32> %c2) { define i1 @foo1_and_commuted(i32 %k, i32 %c1, i32 %c2) { ; CHECK-LABEL: @foo1_and_commuted( ; CHECK-NEXT: [[K2:%.*]] = mul i32 [[K:%.*]], [[K]] -; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]] -; CHECK-NEXT: [[T4:%.*]] = shl i32 1, [[C2:%.*]] +; CHECK-NEXT: [[T:%.*]] = shl nuw i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T4:%.*]] = shl nuw i32 1, [[C2:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]] ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[K2]], [[TMP1]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] @@ -126,8 +126,8 @@ define i1 @foo1_and_commuted(i32 %k, i32 %c1, i32 %c2) { define i1 @foo1_and_commuted_logical(i32 %k, i32 %c1, i32 %c2) { ; CHECK-LABEL: @foo1_and_commuted_logical( ; CHECK-NEXT: [[K2:%.*]] = mul i32 [[K:%.*]], [[K]] -; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]] -; CHECK-NEXT: [[T4:%.*]] = shl i32 1, [[C2:%.*]] +; CHECK-NEXT: [[T:%.*]] = shl nuw i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T4:%.*]] = shl nuw i32 1, [[C2:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T4]] ; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T]], [[TMP1]] ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[K2]], [[TMP2]] @@ -148,8 +148,8 @@ define i1 @foo1_and_commuted_logical(i32 %k, i32 %c1, i32 %c2) { define <2 x i1> @foo1_and_commuted_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i32> %c2) { ; CHECK-LABEL: @foo1_and_commuted_vector( ; CHECK-NEXT: [[K2:%.*]] = mul <2 x i32> [[K:%.*]], [[K]] -; CHECK-NEXT: [[T:%.*]] = shl <2 x i32> , [[C1:%.*]] -; CHECK-NEXT: [[T4:%.*]] = shl <2 x i32> , [[C2:%.*]] +; CHECK-NEXT: [[T:%.*]] = shl nuw <2 x i32> , [[C1:%.*]] +; CHECK-NEXT: [[T4:%.*]] = shl nuw <2 x i32> , [[C2:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[T]], [[T4]] ; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[K2]], [[TMP1]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i32> [[TMP2]], [[TMP1]] @@ -210,8 +210,8 @@ define <2 x i1> @or_consts_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i32> %c2) { define i1 @foo1_or(i32 %k, i32 %c1, i32 %c2) { ; CHECK-LABEL: @foo1_or( -; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]] -; CHECK-NEXT: [[T4:%.*]] = shl i32 1, [[C2:%.*]] +; CHECK-NEXT: [[T:%.*]] = shl nuw i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T4:%.*]] = shl nuw i32 1, [[C2:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]] ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]] @@ -229,8 +229,8 @@ define i1 @foo1_or(i32 %k, i32 %c1, i32 %c2) { define i1 @foo1_or_logical(i32 %k, i32 %c1, i32 %c2) { ; CHECK-LABEL: @foo1_or_logical( -; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]] -; CHECK-NEXT: [[T4:%.*]] = shl i32 1, [[C2:%.*]] +; CHECK-NEXT: [[T:%.*]] = shl nuw i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T4:%.*]] = shl nuw i32 1, [[C2:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T4]] ; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T]], [[TMP1]] ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], [[K:%.*]] @@ -249,8 +249,8 @@ define i1 @foo1_or_logical(i32 %k, i32 %c1, i32 %c2) { define <2 x i1> @foo1_or_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i32> %c2) { ; CHECK-LABEL: @foo1_or_vector( -; CHECK-NEXT: [[T:%.*]] = shl <2 x i32> , [[C1:%.*]] -; CHECK-NEXT: [[T4:%.*]] = shl <2 x i32> , [[C2:%.*]] +; CHECK-NEXT: [[T:%.*]] = shl nuw <2 x i32> , [[C1:%.*]] +; CHECK-NEXT: [[T4:%.*]] = shl nuw <2 x i32> , [[C2:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[T]], [[T4]] ; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], [[K:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq <2 x i32> [[TMP2]], [[TMP1]] @@ -270,8 +270,8 @@ define <2 x i1> @foo1_or_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i32> %c2) { define i1 @foo1_or_commuted(i32 %k, i32 %c1, i32 %c2) { ; CHECK-LABEL: @foo1_or_commuted( ; CHECK-NEXT: [[K2:%.*]] = mul i32 [[K:%.*]], [[K]] -; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]] -; CHECK-NEXT: [[T4:%.*]] = shl i32 1, [[C2:%.*]] +; CHECK-NEXT: [[T:%.*]] = shl nuw i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T4:%.*]] = shl nuw i32 1, [[C2:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]] ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[K2]], [[TMP1]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP2]], [[TMP1]] @@ -291,8 +291,8 @@ define i1 @foo1_or_commuted(i32 %k, i32 %c1, i32 %c2) { define i1 @foo1_or_commuted_logical(i32 %k, i32 %c1, i32 %c2) { ; CHECK-LABEL: @foo1_or_commuted_logical( ; CHECK-NEXT: [[K2:%.*]] = mul i32 [[K:%.*]], [[K]] -; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]] -; CHECK-NEXT: [[T4:%.*]] = shl i32 1, [[C2:%.*]] +; CHECK-NEXT: [[T:%.*]] = shl nuw i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T4:%.*]] = shl nuw i32 1, [[C2:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T4]] ; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T]], [[TMP1]] ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[K2]], [[TMP2]] @@ -313,8 +313,8 @@ define i1 @foo1_or_commuted_logical(i32 %k, i32 %c1, i32 %c2) { define <2 x i1> @foo1_or_commuted_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i32> %c2) { ; CHECK-LABEL: @foo1_or_commuted_vector( ; CHECK-NEXT: [[K2:%.*]] = mul <2 x i32> [[K:%.*]], [[K]] -; CHECK-NEXT: [[T:%.*]] = shl <2 x i32> , [[C1:%.*]] -; CHECK-NEXT: [[T4:%.*]] = shl <2 x i32> , [[C2:%.*]] +; CHECK-NEXT: [[T:%.*]] = shl nuw <2 x i32> , [[C1:%.*]] +; CHECK-NEXT: [[T4:%.*]] = shl nuw <2 x i32> , [[C2:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[T]], [[T4]] ; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[K2]], [[TMP1]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp eq <2 x i32> [[TMP2]], [[TMP1]] @@ -333,7 +333,7 @@ define <2 x i1> @foo1_or_commuted_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i32> define i1 @foo1_and_signbit_lshr(i32 %k, i32 %c1, i32 %c2) { ; CHECK-LABEL: @foo1_and_signbit_lshr( -; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T:%.*]] = shl nuw i32 1, [[C1:%.*]] ; CHECK-NEXT: [[T4:%.*]] = lshr i32 -2147483648, [[C2:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]] ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]] @@ -352,7 +352,7 @@ define i1 @foo1_and_signbit_lshr(i32 %k, i32 %c1, i32 %c2) { define i1 @foo1_and_signbit_lshr_logical(i32 %k, i32 %c1, i32 %c2) { ; CHECK-LABEL: @foo1_and_signbit_lshr_logical( -; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T:%.*]] = shl nuw i32 1, [[C1:%.*]] ; CHECK-NEXT: [[T4:%.*]] = lshr i32 -2147483648, [[C2:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T4]] ; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T]], [[TMP1]] @@ -372,7 +372,7 @@ define i1 @foo1_and_signbit_lshr_logical(i32 %k, i32 %c1, i32 %c2) { define <2 x i1> @foo1_and_signbit_lshr_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i32> %c2) { ; CHECK-LABEL: @foo1_and_signbit_lshr_vector( -; CHECK-NEXT: [[T:%.*]] = shl <2 x i32> , [[C1:%.*]] +; CHECK-NEXT: [[T:%.*]] = shl nuw <2 x i32> , [[C1:%.*]] ; CHECK-NEXT: [[T4:%.*]] = lshr <2 x i32> , [[C2:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[T]], [[T4]] ; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], [[K:%.*]] @@ -391,7 +391,7 @@ define <2 x i1> @foo1_and_signbit_lshr_vector(<2 x i32> %k, <2 x i32> %c1, <2 x define i1 @foo1_or_signbit_lshr(i32 %k, i32 %c1, i32 %c2) { ; CHECK-LABEL: @foo1_or_signbit_lshr( -; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T:%.*]] = shl nuw i32 1, [[C1:%.*]] ; CHECK-NEXT: [[T4:%.*]] = lshr i32 -2147483648, [[C2:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T]], [[T4]] ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]] @@ -410,7 +410,7 @@ define i1 @foo1_or_signbit_lshr(i32 %k, i32 %c1, i32 %c2) { define i1 @foo1_or_signbit_lshr_logical(i32 %k, i32 %c1, i32 %c2) { ; CHECK-LABEL: @foo1_or_signbit_lshr_logical( -; CHECK-NEXT: [[T:%.*]] = shl i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T:%.*]] = shl nuw i32 1, [[C1:%.*]] ; CHECK-NEXT: [[T4:%.*]] = lshr i32 -2147483648, [[C2:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T4]] ; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T]], [[TMP1]] @@ -430,7 +430,7 @@ define i1 @foo1_or_signbit_lshr_logical(i32 %k, i32 %c1, i32 %c2) { define <2 x i1> @foo1_or_signbit_lshr_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i32> %c2) { ; CHECK-LABEL: @foo1_or_signbit_lshr_vector( -; CHECK-NEXT: [[T:%.*]] = shl <2 x i32> , [[C1:%.*]] +; CHECK-NEXT: [[T:%.*]] = shl nuw <2 x i32> , [[C1:%.*]] ; CHECK-NEXT: [[T4:%.*]] = lshr <2 x i32> , [[C2:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or <2 x i32> [[T]], [[T4]] ; CHECK-NEXT: [[TMP2:%.*]] = and <2 x i32> [[TMP1]], [[K:%.*]] @@ -450,7 +450,7 @@ define <2 x i1> @foo1_or_signbit_lshr_vector(<2 x i32> %k, <2 x i32> %c1, <2 x i ; Same as last two, but shift-of-signbit replaced with 'icmp s*' define i1 @foo1_and_signbit_lshr_without_shifting_signbit(i32 %k, i32 %c1, i32 %c2) { ; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]] ; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]] ; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 ; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]] @@ -469,7 +469,7 @@ define i1 @foo1_and_signbit_lshr_without_shifting_signbit(i32 %k, i32 %c1, i32 % define i1 @foo1_and_signbit_lshr_without_shifting_signbit_logical(i32 %k, i32 %c1, i32 %c2) { ; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_logical( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]] ; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]] ; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 ; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]] @@ -488,7 +488,7 @@ define i1 @foo1_and_signbit_lshr_without_shifting_signbit_logical(i32 %k, i32 %c define i1 @foo1_or_signbit_lshr_without_shifting_signbit(i32 %k, i32 %c1, i32 %c2) { ; CHECK-LABEL: @foo1_or_signbit_lshr_without_shifting_signbit( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]] ; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]] ; CHECK-NEXT: [[T2:%.*]] = icmp ne i32 [[T1]], 0 ; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]] @@ -507,7 +507,7 @@ define i1 @foo1_or_signbit_lshr_without_shifting_signbit(i32 %k, i32 %c1, i32 %c define i1 @foo1_or_signbit_lshr_without_shifting_signbit_logical(i32 %k, i32 %c1, i32 %c2) { ; CHECK-LABEL: @foo1_or_signbit_lshr_without_shifting_signbit_logical( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]] ; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]] ; CHECK-NEXT: [[T2:%.*]] = icmp ne i32 [[T1]], 0 ; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]] @@ -614,9 +614,9 @@ define i1 @foo1_or_signbit_lshr_without_shifting_signbit_both_sides_logical(i32 ; Expect to fold define i1 @foo1_and_extra_use_shl(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; CHECK-LABEL: @foo1_and_extra_use_shl( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]] ; CHECK-NEXT: store i32 [[T0]], ptr [[P:%.*]], align 4 -; CHECK-NEXT: [[T1:%.*]] = shl i32 1, [[C2:%.*]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[C2:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T0]], [[T1]] ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i32 [[TMP2]], [[TMP1]] @@ -635,9 +635,9 @@ define i1 @foo1_and_extra_use_shl(i32 %k, i32 %c1, i32 %c2, ptr %p) { define i1 @foo1_and_extra_use_shl_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; CHECK-LABEL: @foo1_and_extra_use_shl_logical( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]] ; CHECK-NEXT: store i32 [[T0]], ptr [[P:%.*]], align 4 -; CHECK-NEXT: [[T1:%.*]] = shl i32 1, [[C2:%.*]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[C2:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T1]] ; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T0]], [[TMP1]] ; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], [[K:%.*]] @@ -658,8 +658,8 @@ define i1 @foo1_and_extra_use_shl_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; Should not fold define i1 @foo1_and_extra_use_and(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; CHECK-LABEL: @foo1_and_extra_use_and( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] -; CHECK-NEXT: [[T1:%.*]] = shl i32 1, [[C2:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[C2:%.*]] ; CHECK-NEXT: [[T2:%.*]] = and i32 [[T0]], [[K:%.*]] ; CHECK-NEXT: store i32 [[T2]], ptr [[P:%.*]], align 4 ; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T0]], [[T1]] @@ -680,8 +680,8 @@ define i1 @foo1_and_extra_use_and(i32 %k, i32 %c1, i32 %c2, ptr %p) { define i1 @foo1_and_extra_use_and_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; CHECK-LABEL: @foo1_and_extra_use_and_logical( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] -; CHECK-NEXT: [[T1:%.*]] = shl i32 1, [[C2:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[C2:%.*]] ; CHECK-NEXT: [[T2:%.*]] = and i32 [[T0]], [[K:%.*]] ; CHECK-NEXT: store i32 [[T2]], ptr [[P:%.*]], align 4 ; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T1]] @@ -704,8 +704,8 @@ define i1 @foo1_and_extra_use_and_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; Should not fold define i1 @foo1_and_extra_use_cmp(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; CHECK-LABEL: @foo1_and_extra_use_cmp( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] -; CHECK-NEXT: [[T1:%.*]] = shl i32 1, [[C2:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[C2:%.*]] ; CHECK-NEXT: [[T2:%.*]] = and i32 [[T0]], [[K:%.*]] ; CHECK-NEXT: [[T3:%.*]] = icmp eq i32 [[T2]], 0 ; CHECK-NEXT: store i1 [[T3]], ptr [[P:%.*]], align 1 @@ -727,8 +727,8 @@ define i1 @foo1_and_extra_use_cmp(i32 %k, i32 %c1, i32 %c2, ptr %p) { define i1 @foo1_and_extra_use_cmp_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; CHECK-LABEL: @foo1_and_extra_use_cmp_logical( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] -; CHECK-NEXT: [[T1:%.*]] = shl i32 1, [[C2:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[C2:%.*]] ; CHECK-NEXT: [[T2:%.*]] = and i32 [[T0]], [[K:%.*]] ; CHECK-NEXT: [[T3:%.*]] = icmp eq i32 [[T2]], 0 ; CHECK-NEXT: store i1 [[T3]], ptr [[P:%.*]], align 1 @@ -752,8 +752,8 @@ define i1 @foo1_and_extra_use_cmp_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; Expect to fold define i1 @foo1_and_extra_use_shl2(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; CHECK-LABEL: @foo1_and_extra_use_shl2( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] -; CHECK-NEXT: [[T1:%.*]] = shl i32 1, [[C2:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[C2:%.*]] ; CHECK-NEXT: store i32 [[T1]], ptr [[P:%.*]], align 4 ; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T0]], [[T1]] ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[K:%.*]] @@ -773,8 +773,8 @@ define i1 @foo1_and_extra_use_shl2(i32 %k, i32 %c1, i32 %c2, ptr %p) { define i1 @foo1_and_extra_use_shl2_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; CHECK-LABEL: @foo1_and_extra_use_shl2_logical( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] -; CHECK-NEXT: [[T1:%.*]] = shl i32 1, [[C2:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[C2:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T1]] ; CHECK-NEXT: store i32 [[TMP1]], ptr [[P:%.*]], align 4 ; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[T0]], [[TMP1]] @@ -796,8 +796,8 @@ define i1 @foo1_and_extra_use_shl2_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; Should not fold define i1 @foo1_and_extra_use_and2(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; CHECK-LABEL: @foo1_and_extra_use_and2( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] -; CHECK-NEXT: [[T1:%.*]] = shl i32 1, [[C2:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[C2:%.*]] ; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[K:%.*]] ; CHECK-NEXT: store i32 [[T4]], ptr [[P:%.*]], align 4 ; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[T0]], [[T1]] @@ -818,8 +818,8 @@ define i1 @foo1_and_extra_use_and2(i32 %k, i32 %c1, i32 %c2, ptr %p) { define i1 @foo1_and_extra_use_and2_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; CHECK-LABEL: @foo1_and_extra_use_and2_logical( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] -; CHECK-NEXT: [[T1:%.*]] = shl i32 1, [[C2:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[C2:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T1]] ; CHECK-NEXT: [[T4:%.*]] = and i32 [[TMP1]], [[K:%.*]] ; CHECK-NEXT: store i32 [[T4]], ptr [[P:%.*]], align 4 @@ -842,8 +842,8 @@ define i1 @foo1_and_extra_use_and2_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; Should not fold define i1 @foo1_and_extra_use_cmp2(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; CHECK-LABEL: @foo1_and_extra_use_cmp2( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] -; CHECK-NEXT: [[T1:%.*]] = shl i32 1, [[C2:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[C2:%.*]] ; CHECK-NEXT: [[T4:%.*]] = and i32 [[T1]], [[K:%.*]] ; CHECK-NEXT: [[T5:%.*]] = icmp eq i32 [[T4]], 0 ; CHECK-NEXT: store i1 [[T5]], ptr [[P:%.*]], align 1 @@ -865,8 +865,8 @@ define i1 @foo1_and_extra_use_cmp2(i32 %k, i32 %c1, i32 %c2, ptr %p) { define i1 @foo1_and_extra_use_cmp2_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; CHECK-LABEL: @foo1_and_extra_use_cmp2_logical( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] -; CHECK-NEXT: [[T1:%.*]] = shl i32 1, [[C2:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[C2:%.*]] ; CHECK-NEXT: [[TMP1:%.*]] = freeze i32 [[T1]] ; CHECK-NEXT: [[T4:%.*]] = and i32 [[TMP1]], [[K:%.*]] ; CHECK-NEXT: [[T5:%.*]] = icmp eq i32 [[T4]], 0 @@ -891,7 +891,7 @@ define i1 @foo1_and_extra_use_cmp2_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; Expect to fold define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_shl1(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_shl1( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]] ; CHECK-NEXT: store i32 [[T0]], ptr [[P:%.*]], align 4 ; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]] ; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 @@ -912,7 +912,7 @@ define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_shl1(i32 %k, define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_shl1_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_shl1_logical( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]] ; CHECK-NEXT: store i32 [[T0]], ptr [[P:%.*]], align 4 ; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]] ; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 @@ -934,7 +934,7 @@ define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_shl1_logical ; Not fold define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_and(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_and( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]] ; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]] ; CHECK-NEXT: store i32 [[T1]], ptr [[P:%.*]], align 4 ; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 @@ -955,7 +955,7 @@ define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_and(i32 %k, define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_and_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_and_logical( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]] ; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]] ; CHECK-NEXT: store i32 [[T1]], ptr [[P:%.*]], align 4 ; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 @@ -977,7 +977,7 @@ define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_and_logical( ; Not fold define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_cmp1(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_cmp1( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]] ; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]] ; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 ; CHECK-NEXT: store i1 [[T2]], ptr [[P:%.*]], align 1 @@ -998,7 +998,7 @@ define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_cmp1(i32 %k, define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_cmp1_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_cmp1_logical( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]] ; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]] ; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 ; CHECK-NEXT: store i1 [[T2]], ptr [[P:%.*]], align 1 @@ -1020,7 +1020,7 @@ define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_cmp1_logical ; Not fold define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_shl2(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_shl2( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]] ; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]] ; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 ; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]] @@ -1041,7 +1041,7 @@ define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_shl2(i32 %k, define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_shl2_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_shl2_logical( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]] ; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]] ; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 ; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]] @@ -1063,7 +1063,7 @@ define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_shl2_logical ; Not fold define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_cmp2(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_cmp2( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]] ; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]] ; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 ; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]] @@ -1084,7 +1084,7 @@ define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_cmp2(i32 %k, define i1 @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_cmp2_logical(i32 %k, i32 %c1, i32 %c2, ptr %p) { ; CHECK-LABEL: @foo1_and_signbit_lshr_without_shifting_signbit_extra_use_cmp2_logical( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[C1:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[C1:%.*]] ; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[K:%.*]] ; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 ; CHECK-NEXT: [[T3:%.*]] = shl i32 [[K]], [[C2:%.*]] diff --git a/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-a.ll b/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-a.ll index f7c0a5d..48b4680 100644 --- a/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-a.ll +++ b/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-after-truncation-variant-a.ll @@ -18,7 +18,7 @@ define i32 @t0_basic(i64 %x, i32 %nbits) { ; CHECK-LABEL: @t0_basic( ; CHECK-NEXT: [[T0:%.*]] = add i32 [[NBITS:%.*]], -1 ; CHECK-NEXT: [[T1:%.*]] = zext i32 [[T0]] to i64 -; CHECK-NEXT: [[T2:%.*]] = shl i64 1, [[T1]] +; CHECK-NEXT: [[T2:%.*]] = shl nuw i64 1, [[T1]] ; CHECK-NEXT: [[T3:%.*]] = add i64 [[T2]], -1 ; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]] ; CHECK-NEXT: call void @use32(i32 [[T0]]) @@ -58,7 +58,7 @@ define <8 x i32> @t1_vec_splat(<8 x i64> %x, <8 x i32> %nbits) { ; CHECK-LABEL: @t1_vec_splat( ; CHECK-NEXT: [[T0:%.*]] = add <8 x i32> [[NBITS:%.*]], ; CHECK-NEXT: [[T1:%.*]] = zext <8 x i32> [[T0]] to <8 x i64> -; CHECK-NEXT: [[T2:%.*]] = shl <8 x i64> , [[T1]] +; CHECK-NEXT: [[T2:%.*]] = shl nuw <8 x i64> , [[T1]] ; CHECK-NEXT: [[T3:%.*]] = add <8 x i64> [[T2]], ; CHECK-NEXT: [[T4:%.*]] = sub <8 x i32> , [[NBITS]] ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]]) @@ -93,7 +93,7 @@ define <8 x i32> @t2_vec_splat_undef(<8 x i64> %x, <8 x i32> %nbits) { ; CHECK-LABEL: @t2_vec_splat_undef( ; CHECK-NEXT: [[T0:%.*]] = add <8 x i32> [[NBITS:%.*]], ; CHECK-NEXT: [[T1:%.*]] = zext <8 x i32> [[T0]] to <8 x i64> -; CHECK-NEXT: [[T2:%.*]] = shl <8 x i64> , [[T1]] +; CHECK-NEXT: [[T2:%.*]] = shl nuw <8 x i64> , [[T1]] ; CHECK-NEXT: [[T3:%.*]] = add <8 x i64> [[T2]], ; CHECK-NEXT: [[T4:%.*]] = sub <8 x i32> , [[NBITS]] ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]]) @@ -128,7 +128,7 @@ define <8 x i32> @t3_vec_nonsplat(<8 x i64> %x, <8 x i32> %nbits) { ; CHECK-LABEL: @t3_vec_nonsplat( ; CHECK-NEXT: [[T0:%.*]] = add <8 x i32> [[NBITS:%.*]], ; CHECK-NEXT: [[T1:%.*]] = zext <8 x i32> [[T0]] to <8 x i64> -; CHECK-NEXT: [[T2:%.*]] = shl <8 x i64> , [[T1]] +; CHECK-NEXT: [[T2:%.*]] = shl nuw <8 x i64> , [[T1]] ; CHECK-NEXT: [[T3:%.*]] = add <8 x i64> [[T2]], ; CHECK-NEXT: [[T4:%.*]] = sub <8 x i32> , [[NBITS]] ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]]) @@ -165,7 +165,7 @@ define i32 @n4_extrause0(i64 %x, i32 %nbits) { ; CHECK-LABEL: @n4_extrause0( ; CHECK-NEXT: [[T0:%.*]] = add i32 [[NBITS:%.*]], -1 ; CHECK-NEXT: [[T1:%.*]] = zext i32 [[T0]] to i64 -; CHECK-NEXT: [[T2:%.*]] = shl i64 1, [[T1]] +; CHECK-NEXT: [[T2:%.*]] = shl nuw i64 1, [[T1]] ; CHECK-NEXT: [[T3:%.*]] = add i64 [[T2]], -1 ; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]] ; CHECK-NEXT: call void @use32(i32 [[T0]]) @@ -201,7 +201,7 @@ define i32 @n5_extrause1(i64 %x, i32 %nbits) { ; CHECK-LABEL: @n5_extrause1( ; CHECK-NEXT: [[T0:%.*]] = add i32 [[NBITS:%.*]], -1 ; CHECK-NEXT: [[T1:%.*]] = zext i32 [[T0]] to i64 -; CHECK-NEXT: [[T2:%.*]] = shl i64 1, [[T1]] +; CHECK-NEXT: [[T2:%.*]] = shl nuw i64 1, [[T1]] ; CHECK-NEXT: [[T3:%.*]] = add i64 [[T2]], -1 ; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]] ; CHECK-NEXT: call void @use32(i32 [[T0]]) @@ -237,7 +237,7 @@ define i32 @n6_extrause2(i64 %x, i32 %nbits) { ; CHECK-LABEL: @n6_extrause2( ; CHECK-NEXT: [[T0:%.*]] = add i32 [[NBITS:%.*]], -1 ; CHECK-NEXT: [[T1:%.*]] = zext i32 [[T0]] to i64 -; CHECK-NEXT: [[T2:%.*]] = shl i64 1, [[T1]] +; CHECK-NEXT: [[T2:%.*]] = shl nuw i64 1, [[T1]] ; CHECK-NEXT: [[T3:%.*]] = add i64 [[T2]], -1 ; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]] ; CHECK-NEXT: call void @use32(i32 [[T0]]) diff --git a/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-a.ll b/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-a.ll index 0ee72b1..c9872b2 100644 --- a/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-a.ll +++ b/llvm/test/Transforms/InstCombine/partally-redundant-left-shift-input-masking-variant-a.ll @@ -16,7 +16,7 @@ declare void @use32(i32) define i32 @t0_basic(i32 %x, i32 %nbits) { ; CHECK-LABEL: @t0_basic( ; CHECK-NEXT: [[T0:%.*]] = add i32 [[NBITS:%.*]], -1 -; CHECK-NEXT: [[T1:%.*]] = shl i32 1, [[T0]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[T0]] ; CHECK-NEXT: [[T2:%.*]] = add i32 [[T1]], -1 ; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]] ; CHECK-NEXT: call void @use32(i32 [[T0]]) @@ -47,7 +47,7 @@ declare void @use8xi32(<8 x i32>) define <8 x i32> @t1_vec_splat(<8 x i32> %x, <8 x i32> %nbits) { ; CHECK-LABEL: @t1_vec_splat( ; CHECK-NEXT: [[T0:%.*]] = add <8 x i32> [[NBITS:%.*]], -; CHECK-NEXT: [[T1:%.*]] = shl <8 x i32> , [[T0]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw <8 x i32> , [[T0]] ; CHECK-NEXT: [[T2:%.*]] = add <8 x i32> [[T1]], ; CHECK-NEXT: [[T4:%.*]] = sub <8 x i32> , [[NBITS]] ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]]) @@ -74,7 +74,7 @@ define <8 x i32> @t1_vec_splat(<8 x i32> %x, <8 x i32> %nbits) { define <8 x i32> @t1_vec_splat_undef(<8 x i32> %x, <8 x i32> %nbits) { ; CHECK-LABEL: @t1_vec_splat_undef( ; CHECK-NEXT: [[T0:%.*]] = add <8 x i32> [[NBITS:%.*]], -; CHECK-NEXT: [[T1:%.*]] = shl <8 x i32> , [[T0]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw <8 x i32> , [[T0]] ; CHECK-NEXT: [[T2:%.*]] = add <8 x i32> [[T1]], ; CHECK-NEXT: [[T4:%.*]] = sub <8 x i32> , [[NBITS]] ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]]) @@ -101,7 +101,7 @@ define <8 x i32> @t1_vec_splat_undef(<8 x i32> %x, <8 x i32> %nbits) { define <8 x i32> @t2_vec_nonsplat(<8 x i32> %x, <8 x i32> %nbits) { ; CHECK-LABEL: @t2_vec_nonsplat( ; CHECK-NEXT: [[T0:%.*]] = add <8 x i32> [[NBITS:%.*]], -; CHECK-NEXT: [[T1:%.*]] = shl <8 x i32> , [[T0]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw <8 x i32> , [[T0]] ; CHECK-NEXT: [[T2:%.*]] = add <8 x i32> [[T1]], ; CHECK-NEXT: [[T4:%.*]] = sub <8 x i32> , [[NBITS]] ; CHECK-NEXT: call void @use8xi32(<8 x i32> [[T0]]) @@ -130,7 +130,7 @@ define <8 x i32> @t2_vec_nonsplat(<8 x i32> %x, <8 x i32> %nbits) { define i32 @n3_extrause(i32 %x, i32 %nbits) { ; CHECK-LABEL: @n3_extrause( ; CHECK-NEXT: [[T0:%.*]] = add i32 [[NBITS:%.*]], -1 -; CHECK-NEXT: [[T1:%.*]] = shl i32 1, [[T0]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[T0]] ; CHECK-NEXT: [[T2:%.*]] = add i32 [[T1]], -1 ; CHECK-NEXT: [[T3:%.*]] = and i32 [[T2]], [[X:%.*]] ; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]] diff --git a/llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-a.ll b/llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-a.ll index 8b876e0a4..d177a2b 100644 --- a/llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-a.ll +++ b/llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-after-truncation-variant-a.ll @@ -17,7 +17,7 @@ declare void @use64(i64) define i32 @t0_basic(i64 %x, i32 %nbits) { ; CHECK-LABEL: @t0_basic( ; CHECK-NEXT: [[T0:%.*]] = zext i32 [[NBITS:%.*]] to i64 -; CHECK-NEXT: [[T1:%.*]] = shl i64 1, [[T0]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw i64 1, [[T0]] ; CHECK-NEXT: [[T2:%.*]] = add i64 [[T1]], -1 ; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]] ; CHECK-NEXT: [[T4:%.*]] = and i64 [[T2]], [[X:%.*]] @@ -57,7 +57,7 @@ declare void @use8xi64(<8 x i64>) define <8 x i32> @t1_vec_splat(<8 x i64> %x, <8 x i32> %nbits) { ; CHECK-LABEL: @t1_vec_splat( ; CHECK-NEXT: [[T0:%.*]] = zext <8 x i32> [[NBITS:%.*]] to <8 x i64> -; CHECK-NEXT: [[T1:%.*]] = shl <8 x i64> , [[T0]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw <8 x i64> , [[T0]] ; CHECK-NEXT: [[T2:%.*]] = add <8 x i64> [[T1]], ; CHECK-NEXT: [[T3:%.*]] = sub <8 x i32> , [[NBITS]] ; CHECK-NEXT: [[T4:%.*]] = and <8 x i64> [[T2]], [[X:%.*]] @@ -92,7 +92,7 @@ define <8 x i32> @t1_vec_splat(<8 x i64> %x, <8 x i32> %nbits) { define <8 x i32> @t2_vec_splat_undef(<8 x i64> %x, <8 x i32> %nbits) { ; CHECK-LABEL: @t2_vec_splat_undef( ; CHECK-NEXT: [[T0:%.*]] = zext <8 x i32> [[NBITS:%.*]] to <8 x i64> -; CHECK-NEXT: [[T1:%.*]] = shl <8 x i64> , [[T0]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw <8 x i64> , [[T0]] ; CHECK-NEXT: [[T2:%.*]] = add <8 x i64> [[T1]], ; CHECK-NEXT: [[T3:%.*]] = sub <8 x i32> , [[NBITS]] ; CHECK-NEXT: [[T4:%.*]] = and <8 x i64> [[T2]], [[X:%.*]] @@ -127,7 +127,7 @@ define <8 x i32> @t2_vec_splat_undef(<8 x i64> %x, <8 x i32> %nbits) { define <8 x i32> @t3_vec_nonsplat(<8 x i64> %x, <8 x i32> %nbits) { ; CHECK-LABEL: @t3_vec_nonsplat( ; CHECK-NEXT: [[T0:%.*]] = zext <8 x i32> [[NBITS:%.*]] to <8 x i64> -; CHECK-NEXT: [[T1:%.*]] = shl <8 x i64> , [[T0]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw <8 x i64> , [[T0]] ; CHECK-NEXT: [[T2:%.*]] = add <8 x i64> [[T1]], ; CHECK-NEXT: [[T3:%.*]] = sub <8 x i32> , [[NBITS]] ; CHECK-NEXT: [[T4:%.*]] = and <8 x i64> [[T2]], [[X:%.*]] @@ -164,7 +164,7 @@ define <8 x i32> @t3_vec_nonsplat(<8 x i64> %x, <8 x i32> %nbits) { define i32 @n4_extrause(i64 %x, i32 %nbits) { ; CHECK-LABEL: @n4_extrause( ; CHECK-NEXT: [[T0:%.*]] = zext i32 [[NBITS:%.*]] to i64 -; CHECK-NEXT: [[T1:%.*]] = shl i64 1, [[T0]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw i64 1, [[T0]] ; CHECK-NEXT: [[T2:%.*]] = add i64 [[T1]], -1 ; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]] ; CHECK-NEXT: [[T4:%.*]] = and i64 [[T2]], [[X:%.*]] diff --git a/llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-a.ll b/llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-a.ll index a935e1e..d15e3a1 100644 --- a/llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-a.ll +++ b/llvm/test/Transforms/InstCombine/redundant-left-shift-input-masking-variant-a.ll @@ -17,7 +17,7 @@ declare void @use32(i32) define i32 @t0_basic(i32 %x, i32 %nbits) { ; CHECK-LABEL: @t0_basic( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[NBITS:%.*]] ; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], -1 ; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]] ; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]] @@ -42,7 +42,7 @@ define i32 @t0_basic(i32 %x, i32 %nbits) { define i32 @t1_bigger_shift(i32 %x, i32 %nbits) { ; CHECK-LABEL: @t1_bigger_shift( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[NBITS:%.*]] ; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], -1 ; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]] ; CHECK-NEXT: [[T3:%.*]] = sub i32 33, [[NBITS]] @@ -68,7 +68,7 @@ define i32 @t1_bigger_shift(i32 %x, i32 %nbits) { define i32 @t2_bigger_mask(i32 %x, i32 %nbits) { ; CHECK-LABEL: @t2_bigger_mask( ; CHECK-NEXT: [[T0:%.*]] = add i32 [[NBITS:%.*]], 1 -; CHECK-NEXT: [[T1:%.*]] = shl i32 1, [[T0]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[T0]] ; CHECK-NEXT: [[T2:%.*]] = add nsw i32 [[T1]], -1 ; CHECK-NEXT: [[T3:%.*]] = and i32 [[T2]], [[X:%.*]] ; CHECK-NEXT: [[T4:%.*]] = sub i32 32, [[NBITS]] @@ -100,7 +100,7 @@ declare void @use3xi32(<3 x i32>) define <3 x i32> @t3_vec_splat(<3 x i32> %x, <3 x i32> %nbits) { ; CHECK-LABEL: @t3_vec_splat( -; CHECK-NEXT: [[T1:%.*]] = shl <3 x i32> , [[NBITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw <3 x i32> , [[NBITS:%.*]] ; CHECK-NEXT: [[T2:%.*]] = add nsw <3 x i32> [[T1]], ; CHECK-NEXT: [[T3:%.*]] = and <3 x i32> [[T2]], [[X:%.*]] ; CHECK-NEXT: [[T4:%.*]] = sub <3 x i32> , [[NBITS]] @@ -129,7 +129,7 @@ define <3 x i32> @t3_vec_splat(<3 x i32> %x, <3 x i32> %nbits) { define <3 x i32> @t4_vec_nonsplat(<3 x i32> %x, <3 x i32> %nbits) { ; CHECK-LABEL: @t4_vec_nonsplat( ; CHECK-NEXT: [[T0:%.*]] = add <3 x i32> [[NBITS:%.*]], -; CHECK-NEXT: [[T1:%.*]] = shl <3 x i32> , [[T0]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw <3 x i32> , [[T0]] ; CHECK-NEXT: [[T2:%.*]] = add nsw <3 x i32> [[T1]], ; CHECK-NEXT: [[T3:%.*]] = and <3 x i32> [[T2]], [[X:%.*]] ; CHECK-NEXT: [[T4:%.*]] = sub <3 x i32> , [[NBITS]] @@ -157,7 +157,7 @@ define <3 x i32> @t4_vec_nonsplat(<3 x i32> %x, <3 x i32> %nbits) { define <3 x i32> @t5_vec_undef(<3 x i32> %x, <3 x i32> %nbits) { ; CHECK-LABEL: @t5_vec_undef( -; CHECK-NEXT: [[T1:%.*]] = shl <3 x i32> , [[NBITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw <3 x i32> , [[NBITS:%.*]] ; CHECK-NEXT: [[T2:%.*]] = add nsw <3 x i32> [[T1]], ; CHECK-NEXT: [[T3:%.*]] = and <3 x i32> [[T2]], [[X:%.*]] ; CHECK-NEXT: [[T4:%.*]] = sub <3 x i32> , [[NBITS]] @@ -190,7 +190,7 @@ declare i32 @gen32() define i32 @t6_commutativity0(i32 %nbits) { ; CHECK-LABEL: @t6_commutativity0( ; CHECK-NEXT: [[X:%.*]] = call i32 @gen32() -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[NBITS:%.*]] ; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], -1 ; CHECK-NEXT: [[T2:%.*]] = and i32 [[X]], [[T1]] ; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]] @@ -216,9 +216,9 @@ define i32 @t6_commutativity0(i32 %nbits) { define i32 @t7_commutativity1(i32 %nbits0, i32 %nbits1) { ; CHECK-LABEL: @t7_commutativity1( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS0:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[NBITS0:%.*]] ; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], -1 -; CHECK-NEXT: [[T2:%.*]] = shl i32 1, [[NBITS1:%.*]] +; CHECK-NEXT: [[T2:%.*]] = shl nuw i32 1, [[NBITS1:%.*]] ; CHECK-NEXT: [[T3:%.*]] = add nsw i32 [[T2]], -1 ; CHECK-NEXT: [[T4:%.*]] = and i32 [[T3]], [[T1]] ; CHECK-NEXT: [[T5:%.*]] = sub i32 32, [[NBITS0]] @@ -248,9 +248,9 @@ define i32 @t7_commutativity1(i32 %nbits0, i32 %nbits1) { } define i32 @t8_commutativity2(i32 %nbits0, i32 %nbits1) { ; CHECK-LABEL: @t8_commutativity2( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS0:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[NBITS0:%.*]] ; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], -1 -; CHECK-NEXT: [[T2:%.*]] = shl i32 1, [[NBITS1:%.*]] +; CHECK-NEXT: [[T2:%.*]] = shl nuw i32 1, [[NBITS1:%.*]] ; CHECK-NEXT: [[T3:%.*]] = add nsw i32 [[T2]], -1 ; CHECK-NEXT: [[T4:%.*]] = and i32 [[T3]], [[T1]] ; CHECK-NEXT: [[T5:%.*]] = sub i32 32, [[NBITS1]] @@ -283,7 +283,7 @@ define i32 @t8_commutativity2(i32 %nbits0, i32 %nbits1) { define i32 @t9_nuw(i32 %x, i32 %nbits) { ; CHECK-LABEL: @t9_nuw( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[NBITS:%.*]] ; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], -1 ; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]] ; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]] @@ -308,7 +308,7 @@ define i32 @t9_nuw(i32 %x, i32 %nbits) { define i32 @t10_nsw(i32 %x, i32 %nbits) { ; CHECK-LABEL: @t10_nsw( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[NBITS:%.*]] ; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], -1 ; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]] ; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]] @@ -333,7 +333,7 @@ define i32 @t10_nsw(i32 %x, i32 %nbits) { define i32 @t11_nuw_nsw(i32 %x, i32 %nbits) { ; CHECK-LABEL: @t11_nuw_nsw( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[NBITS:%.*]] ; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], -1 ; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]] ; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]] @@ -385,8 +385,8 @@ define i32 @n12_not_minus_one(i32 %x, i32 %nbits) { define i32 @n13_not_minus_one(i32 %x, i32 %nbits) { ; CHECK-LABEL: @n13_not_minus_one( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[NBITS:%.*]] -; CHECK-NEXT: [[T1:%.*]] = add nsw i32 [[T0]], 2147483647 +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[NBITS:%.*]] +; CHECK-NEXT: [[T1:%.*]] = add nuw nsw i32 [[T0]], 2147483647 ; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[X:%.*]] ; CHECK-NEXT: [[T3:%.*]] = sub i32 32, [[NBITS]] ; CHECK-NEXT: call void @use32(i32 [[T0]]) diff --git a/llvm/test/Transforms/InstCombine/rem.ll b/llvm/test/Transforms/InstCombine/rem.ll index 26b2316..5ab4b7b 100644 --- a/llvm/test/Transforms/InstCombine/rem.ll +++ b/llvm/test/Transforms/InstCombine/rem.ll @@ -335,7 +335,7 @@ define i32 @test13(i32 %i) { define i64 @test14(i64 %x, i32 %y) { ; CHECK-LABEL: @test14( -; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, [[Y:%.*]] +; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, [[Y:%.*]] ; CHECK-NEXT: [[ZEXT:%.*]] = zext i32 [[SHL]] to i64 ; CHECK-NEXT: [[TMP1:%.*]] = add nsw i64 [[ZEXT]], -1 ; CHECK-NEXT: [[UREM:%.*]] = and i64 [[TMP1]], [[X:%.*]] @@ -404,8 +404,8 @@ define i32 @test18(i16 %x, i32 %y) { define i32 @test19(i32 %x, i32 %y) { ; CHECK-LABEL: @test19( -; CHECK-NEXT: [[A:%.*]] = shl i32 1, [[X:%.*]] -; CHECK-NEXT: [[B:%.*]] = shl i32 1, [[Y:%.*]] +; CHECK-NEXT: [[A:%.*]] = shl nuw i32 1, [[X:%.*]] +; CHECK-NEXT: [[B:%.*]] = shl nuw i32 1, [[Y:%.*]] ; CHECK-NEXT: [[C:%.*]] = and i32 [[A]], [[B]] ; CHECK-NEXT: [[D:%.*]] = add i32 [[C]], [[A]] ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[D]], -1 @@ -422,8 +422,8 @@ define i32 @test19(i32 %x, i32 %y) { define i32 @test19_commutative0(i32 %x, i32 %y) { ; CHECK-LABEL: @test19_commutative0( -; CHECK-NEXT: [[A:%.*]] = shl i32 1, [[X:%.*]] -; CHECK-NEXT: [[B:%.*]] = shl i32 1, [[Y:%.*]] +; CHECK-NEXT: [[A:%.*]] = shl nuw i32 1, [[X:%.*]] +; CHECK-NEXT: [[B:%.*]] = shl nuw i32 1, [[Y:%.*]] ; CHECK-NEXT: [[C:%.*]] = and i32 [[B]], [[A]] ; CHECK-NEXT: [[D:%.*]] = add i32 [[C]], [[A]] ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[D]], -1 @@ -440,8 +440,8 @@ define i32 @test19_commutative0(i32 %x, i32 %y) { define i32 @test19_commutative1(i32 %x, i32 %y) { ; CHECK-LABEL: @test19_commutative1( -; CHECK-NEXT: [[A:%.*]] = shl i32 1, [[X:%.*]] -; CHECK-NEXT: [[B:%.*]] = shl i32 1, [[Y:%.*]] +; CHECK-NEXT: [[A:%.*]] = shl nuw i32 1, [[X:%.*]] +; CHECK-NEXT: [[B:%.*]] = shl nuw i32 1, [[Y:%.*]] ; CHECK-NEXT: [[C:%.*]] = and i32 [[A]], [[B]] ; CHECK-NEXT: [[D:%.*]] = add i32 [[A]], [[C]] ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[D]], -1 @@ -458,8 +458,8 @@ define i32 @test19_commutative1(i32 %x, i32 %y) { define i32 @test19_commutative2(i32 %x, i32 %y) { ; CHECK-LABEL: @test19_commutative2( -; CHECK-NEXT: [[A:%.*]] = shl i32 1, [[X:%.*]] -; CHECK-NEXT: [[B:%.*]] = shl i32 1, [[Y:%.*]] +; CHECK-NEXT: [[A:%.*]] = shl nuw i32 1, [[X:%.*]] +; CHECK-NEXT: [[B:%.*]] = shl nuw i32 1, [[Y:%.*]] ; CHECK-NEXT: [[C:%.*]] = and i32 [[B]], [[A]] ; CHECK-NEXT: [[D:%.*]] = add i32 [[A]], [[C]] ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[D]], -1 @@ -490,10 +490,10 @@ define i32 @test21(i1 %c0, ptr %p) { ; CHECK-NEXT: br i1 [[C0:%.*]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] ; CHECK: if.then: ; CHECK-NEXT: [[V:%.*]] = load volatile i32, ptr [[P:%.*]], align 4 -; CHECK-NEXT: [[PHI_BO:%.*]] = srem i32 [[V]], 5 +; CHECK-NEXT: [[TMP0:%.*]] = srem i32 [[V]], 5 ; CHECK-NEXT: br label [[IF_END]] ; CHECK: if.end: -; CHECK-NEXT: [[LHS:%.*]] = phi i32 [ [[PHI_BO]], [[IF_THEN]] ], [ 0, [[ENTRY:%.*]] ] +; CHECK-NEXT: [[LHS:%.*]] = phi i32 [ [[TMP0]], [[IF_THEN]] ], [ 0, [[ENTRY:%.*]] ] ; CHECK-NEXT: ret i32 [[LHS]] ; entry: @@ -619,10 +619,10 @@ define i32 @pr27968_3(i1 %c0, i1 %always_false, ptr %p) { ; CHECK-NEXT: br i1 [[C0:%.*]], label [[IF_THEN:%.*]], label [[IF_END:%.*]] ; CHECK: if.then: ; CHECK-NEXT: [[V:%.*]] = load volatile i32, ptr [[P:%.*]], align 4 -; CHECK-NEXT: [[PHI_BO:%.*]] = and i32 [[V]], 2147483647 +; CHECK-NEXT: [[TMP0:%.*]] = and i32 [[V]], 2147483647 ; CHECK-NEXT: br label [[IF_END]] ; CHECK: if.end: -; CHECK-NEXT: [[LHS:%.*]] = phi i32 [ [[PHI_BO]], [[IF_THEN]] ], [ 5, [[ENTRY:%.*]] ] +; CHECK-NEXT: [[LHS:%.*]] = phi i32 [ [[TMP0]], [[IF_THEN]] ], [ 5, [[ENTRY:%.*]] ] ; CHECK-NEXT: br i1 [[ALWAYS_FALSE:%.*]], label [[REM_IS_SAFE:%.*]], label [[REM_IS_UNSAFE:%.*]] ; CHECK: rem.is.safe: ; CHECK-NEXT: ret i32 [[LHS]] diff --git a/llvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll b/llvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll index 0433bad..0c4525a 100644 --- a/llvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll +++ b/llvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll @@ -221,10 +221,10 @@ define i4 @PR45762(i3 %x4) { ; CHECK-LABEL: @PR45762( ; CHECK-NEXT: [[T4:%.*]] = call i3 @llvm.cttz.i3(i3 [[X4:%.*]], i1 false), !range [[RNG2:![0-9]+]] ; CHECK-NEXT: [[T7:%.*]] = zext i3 [[T4]] to i4 -; CHECK-NEXT: [[ONE_HOT_16:%.*]] = shl i4 1, [[T7]] +; CHECK-NEXT: [[ONE_HOT_16:%.*]] = shl nuw i4 1, [[T7]] ; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i3 [[X4]], 0 -; CHECK-NEXT: [[UMUL_23:%.*]] = select i1 [[DOTNOT]], i4 0, i4 [[T7]] -; CHECK-NEXT: [[SEL_71:%.*]] = shl i4 [[ONE_HOT_16]], [[UMUL_23]] +; CHECK-NEXT: [[UMUL_231:%.*]] = select i1 [[DOTNOT]], i4 0, i4 [[T7]] +; CHECK-NEXT: [[SEL_71:%.*]] = shl i4 [[ONE_HOT_16]], [[UMUL_231]] ; CHECK-NEXT: ret i4 [[SEL_71]] ; %t4 = call i3 @llvm.cttz.i3(i3 %x4, i1 false) @@ -250,10 +250,10 @@ define i4 @PR45762_logical(i3 %x4) { ; CHECK-LABEL: @PR45762_logical( ; CHECK-NEXT: [[T4:%.*]] = call i3 @llvm.cttz.i3(i3 [[X4:%.*]], i1 false), !range [[RNG2]] ; CHECK-NEXT: [[T7:%.*]] = zext i3 [[T4]] to i4 -; CHECK-NEXT: [[ONE_HOT_16:%.*]] = shl i4 1, [[T7]] +; CHECK-NEXT: [[ONE_HOT_16:%.*]] = shl nuw i4 1, [[T7]] ; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i3 [[X4]], 0 -; CHECK-NEXT: [[UMUL_23:%.*]] = select i1 [[DOTNOT]], i4 0, i4 [[T7]] -; CHECK-NEXT: [[SEL_71:%.*]] = shl i4 [[ONE_HOT_16]], [[UMUL_23]] +; CHECK-NEXT: [[UMUL_231:%.*]] = select i1 [[DOTNOT]], i4 0, i4 [[T7]] +; CHECK-NEXT: [[SEL_71:%.*]] = shl i4 [[ONE_HOT_16]], [[UMUL_231]] ; CHECK-NEXT: ret i4 [[SEL_71]] ; %t4 = call i3 @llvm.cttz.i3(i3 %x4, i1 false) diff --git a/llvm/test/Transforms/InstCombine/set-lowbits-mask-canonicalize.ll b/llvm/test/Transforms/InstCombine/set-lowbits-mask-canonicalize.ll index 2476406..3ee0224 100644 --- a/llvm/test/Transforms/InstCombine/set-lowbits-mask-canonicalize.ll +++ b/llvm/test/Transforms/InstCombine/set-lowbits-mask-canonicalize.ll @@ -238,7 +238,7 @@ declare void @use32(i32) ; One use only. define i32 @bad_oneuse0(i32 %NBits) { ; CHECK-LABEL: @bad_oneuse0( -; CHECK-NEXT: [[SETBIT:%.*]] = shl i32 1, [[NBITS:%.*]] +; CHECK-NEXT: [[SETBIT:%.*]] = shl nuw i32 1, [[NBITS:%.*]] ; CHECK-NEXT: call void @use32(i32 [[SETBIT]]) ; CHECK-NEXT: [[RET:%.*]] = add i32 [[SETBIT]], -1 ; CHECK-NEXT: ret i32 [[RET]] @@ -266,7 +266,7 @@ define i32 @bad_shl(i32 %base, i32 %NBits) { define i32 @bad_add0(i32 %NBits, i32 %addop2) { ; CHECK-LABEL: @bad_add0( -; CHECK-NEXT: [[SETBIT:%.*]] = shl i32 1, [[NBITS:%.*]] +; CHECK-NEXT: [[SETBIT:%.*]] = shl nuw i32 1, [[NBITS:%.*]] ; CHECK-NEXT: [[RET:%.*]] = add i32 [[SETBIT]], [[ADDOP2:%.*]] ; CHECK-NEXT: ret i32 [[RET]] ; @@ -279,8 +279,8 @@ define i32 @bad_add0(i32 %NBits, i32 %addop2) { define i32 @bad_add1(i32 %NBits) { ; CHECK-LABEL: @bad_add1( -; CHECK-NEXT: [[SETBIT:%.*]] = shl i32 1, [[NBITS:%.*]] -; CHECK-NEXT: [[RET:%.*]] = add i32 [[SETBIT]], 1 +; CHECK-NEXT: [[SETBIT:%.*]] = shl nuw i32 1, [[NBITS:%.*]] +; CHECK-NEXT: [[RET:%.*]] = add nuw i32 [[SETBIT]], 1 ; CHECK-NEXT: ret i32 [[RET]] ; %setbit = shl i32 1, %NBits @@ -290,7 +290,7 @@ define i32 @bad_add1(i32 %NBits) { define i32 @bad_add2(i32 %NBits) { ; CHECK-LABEL: @bad_add2( -; CHECK-NEXT: [[SETBIT:%.*]] = shl i32 1, [[NBITS:%.*]] +; CHECK-NEXT: [[SETBIT:%.*]] = shl nuw i32 1, [[NBITS:%.*]] ; CHECK-NEXT: [[RET:%.*]] = add i32 [[SETBIT]], -2 ; CHECK-NEXT: ret i32 [[RET]] ; diff --git a/llvm/test/Transforms/InstCombine/shift-add.ll b/llvm/test/Transforms/InstCombine/shift-add.ll index 97c5470..2007c63 100644 --- a/llvm/test/Transforms/InstCombine/shift-add.ll +++ b/llvm/test/Transforms/InstCombine/shift-add.ll @@ -355,7 +355,7 @@ define <2 x i7> @ashr_exact_add_negative_leading_ones_vec(<2 x i7> %x) { define i32 @shl_nsw_add_negative(i32 %x) { ; CHECK-LABEL: @shl_nsw_add_negative( -; CHECK-NEXT: [[R:%.*]] = shl i32 1, [[X:%.*]] +; CHECK-NEXT: [[R:%.*]] = shl nuw i32 1, [[X:%.*]] ; CHECK-NEXT: ret i32 [[R]] ; %a = add i32 %x, -1 diff --git a/llvm/test/Transforms/InstCombine/shift-direction-in-bit-test.ll b/llvm/test/Transforms/InstCombine/shift-direction-in-bit-test.ll index 455cc6f..a8f4644 100644 --- a/llvm/test/Transforms/InstCombine/shift-direction-in-bit-test.ll +++ b/llvm/test/Transforms/InstCombine/shift-direction-in-bit-test.ll @@ -126,7 +126,7 @@ define i1 @t6_twoshifts1(i32 %a, i32 %b, i32 %c, i32 %d) { define i1 @t7_twoshifts2(i32 %a, i32 %b, i32 %c, i32 %d) { ; CHECK-LABEL: @t7_twoshifts2( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[B:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[B:%.*]] ; CHECK-NEXT: [[T1:%.*]] = shl i32 [[C:%.*]], [[D:%.*]] ; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[T0]] ; CHECK-NEXT: [[T3:%.*]] = icmp eq i32 [[T2]], 0 @@ -142,7 +142,7 @@ define i1 @t7_twoshifts2(i32 %a, i32 %b, i32 %c, i32 %d) { define i1 @t8_twoshifts3(i32 %a, i32 %b, i32 %c, i32 %d) { ; CHECK-LABEL: @t8_twoshifts3( ; CHECK-NEXT: [[T0:%.*]] = shl i32 [[A:%.*]], [[B:%.*]] -; CHECK-NEXT: [[T1:%.*]] = shl i32 1, [[D:%.*]] +; CHECK-NEXT: [[T1:%.*]] = shl nuw i32 1, [[D:%.*]] ; CHECK-NEXT: [[T2:%.*]] = and i32 [[T1]], [[T0]] ; CHECK-NEXT: [[T3:%.*]] = icmp eq i32 [[T2]], 0 ; CHECK-NEXT: ret i1 [[T3]] @@ -213,7 +213,7 @@ define i1 @t11_extrause2(i32 %x, i32 %y, i32 %z) { define i1 @t12_shift_of_const0(i32 %x, i32 %y, i32 %z) { ; CHECK-LABEL: @t12_shift_of_const0( -; CHECK-NEXT: [[T0:%.*]] = shl i32 1, [[Y:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i32 1, [[Y:%.*]] ; CHECK-NEXT: [[T1:%.*]] = and i32 [[T0]], [[Z:%.*]] ; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[T1]], 0 ; CHECK-NEXT: ret i1 [[T2]] @@ -250,7 +250,7 @@ define i1 @t14_and_with_const0(i32 %x, i32 %y, i32 %z) { } define i1 @t15_and_with_const1(i32 %x, i32 %y, i32 %z) { ; CHECK-LABEL: @t15_and_with_const1( -; CHECK-NEXT: [[TMP1:%.*]] = shl i32 1, [[Y:%.*]] +; CHECK-NEXT: [[TMP1:%.*]] = shl nuw i32 1, [[Y:%.*]] ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], [[X:%.*]] ; CHECK-NEXT: [[T2:%.*]] = icmp eq i32 [[TMP2]], 0 ; CHECK-NEXT: ret i1 [[T2]] diff --git a/llvm/test/Transforms/InstCombine/shift.ll b/llvm/test/Transforms/InstCombine/shift.ll index eb5e37b..710ae11 100644 --- a/llvm/test/Transforms/InstCombine/shift.ll +++ b/llvm/test/Transforms/InstCombine/shift.ll @@ -602,7 +602,7 @@ define <2 x i32> @shl_nuw_nsw_splat_vec(<2 x i8> %x) { define i32 @test38(i32 %x) nounwind readnone { ; CHECK-LABEL: @test38( ; CHECK-NEXT: [[REM1:%.*]] = and i32 [[X:%.*]], 31 -; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, [[REM1]] +; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, [[REM1]] ; CHECK-NEXT: ret i32 [[SHL]] ; %rem = srem i32 %x, 32 @@ -613,7 +613,7 @@ define i32 @test38(i32 %x) nounwind readnone { define <2 x i32> @test38_uniform(<2 x i32> %x) nounwind readnone { ; CHECK-LABEL: @test38_uniform( ; CHECK-NEXT: [[REM1:%.*]] = and <2 x i32> [[X:%.*]], -; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> , [[REM1]] +; CHECK-NEXT: [[SHL:%.*]] = shl nuw <2 x i32> , [[REM1]] ; CHECK-NEXT: ret <2 x i32> [[SHL]] ; %rem = srem <2 x i32> %x, @@ -624,7 +624,7 @@ define <2 x i32> @test38_uniform(<2 x i32> %x) nounwind readnone { define <3 x i32> @test38_nonuniform(<3 x i32> %x) nounwind readnone { ; CHECK-LABEL: @test38_nonuniform( ; CHECK-NEXT: [[REM1:%.*]] = and <3 x i32> [[X:%.*]], -; CHECK-NEXT: [[SHL:%.*]] = shl <3 x i32> , [[REM1]] +; CHECK-NEXT: [[SHL:%.*]] = shl nuw <3 x i32> , [[REM1]] ; CHECK-NEXT: ret <3 x i32> [[SHL]] ; %rem = srem <3 x i32> %x, @@ -1360,8 +1360,8 @@ define <2 x i8> @ashr_demanded_bits_splat(<2 x i8> %x) { define @ashr_demanded_bits_splat2( %x) { ; CHECK-LABEL: @ashr_demanded_bits_splat2( -; CHECK-NEXT: [[AND:%.*]] = ashr [[X:%.*]], shufflevector ( insertelement ( poison, i8 7, i32 0), poison, zeroinitializer) -; CHECK-NEXT: ret [[AND]] +; CHECK-NEXT: [[SHR:%.*]] = ashr [[X:%.*]], shufflevector ( insertelement ( poison, i8 7, i32 0), poison, zeroinitializer) +; CHECK-NEXT: ret [[SHR]] ; %and = and %x, shufflevector ( insertelement ( poison, i8 128, i32 0), poison, zeroinitializer) %shr = ashr %and, shufflevector ( insertelement ( poison, i8 7, i32 0), poison, zeroinitializer) @@ -1380,8 +1380,8 @@ define <2 x i8> @lshr_demanded_bits_splat(<2 x i8> %x) { define @lshr_demanded_bits_splat2( %x) { ; CHECK-LABEL: @lshr_demanded_bits_splat2( -; CHECK-NEXT: [[AND:%.*]] = lshr [[X:%.*]], shufflevector ( insertelement ( poison, i8 7, i32 0), poison, zeroinitializer) -; CHECK-NEXT: ret [[AND]] +; CHECK-NEXT: [[SHR:%.*]] = lshr [[X:%.*]], shufflevector ( insertelement ( poison, i8 7, i32 0), poison, zeroinitializer) +; CHECK-NEXT: ret [[SHR]] ; %and = and %x, shufflevector ( insertelement ( poison, i8 128, i32 0), poison, zeroinitializer) %shr = lshr %and, shufflevector ( insertelement ( poison, i8 7, i32 0), poison, zeroinitializer) diff --git a/llvm/test/Transforms/InstCombine/shl-sub.ll b/llvm/test/Transforms/InstCombine/shl-sub.ll index 8bdc3bf..7cecd33 100644 --- a/llvm/test/Transforms/InstCombine/shl-sub.ll +++ b/llvm/test/Transforms/InstCombine/shl-sub.ll @@ -71,7 +71,7 @@ define <3 x i64> @shl_sub_i64_vec_undef(<3 x i64> %x) { define i32 @shl_bad_sub_i32(i32 %x) { ; CHECK-LABEL: @shl_bad_sub_i32( ; CHECK-NEXT: [[S:%.*]] = sub i32 32, [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = shl i32 1, [[S]] +; CHECK-NEXT: [[R:%.*]] = shl nuw i32 1, [[S]] ; CHECK-NEXT: ret i32 [[R]] ; %s = sub i32 32, %x @@ -93,7 +93,7 @@ define i32 @bad_shl_sub_i32(i32 %x) { define i32 @shl_bad_sub2_i32(i32 %x) { ; CHECK-LABEL: @shl_bad_sub2_i32( ; CHECK-NEXT: [[S:%.*]] = add i32 [[X:%.*]], -31 -; CHECK-NEXT: [[R:%.*]] = shl i32 1, [[S]] +; CHECK-NEXT: [[R:%.*]] = shl nuw i32 1, [[S]] ; CHECK-NEXT: ret i32 [[R]] ; %s = sub i32 %x, 31 @@ -104,7 +104,7 @@ define i32 @shl_bad_sub2_i32(i32 %x) { define i32 @bad_shl2_sub_i32(i32 %x) { ; CHECK-LABEL: @bad_shl2_sub_i32( ; CHECK-NEXT: [[S:%.*]] = add i32 [[X:%.*]], -31 -; CHECK-NEXT: [[R:%.*]] = shl i32 1, [[S]] +; CHECK-NEXT: [[R:%.*]] = shl nuw i32 1, [[S]] ; CHECK-NEXT: ret i32 [[R]] ; %s = sub i32 %x, 31 @@ -115,7 +115,7 @@ define i32 @bad_shl2_sub_i32(i32 %x) { define i8 @shl_bad_sub_i8(i8 %x) { ; CHECK-LABEL: @shl_bad_sub_i8( ; CHECK-NEXT: [[S:%.*]] = sub i8 4, [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = shl i8 1, [[S]] +; CHECK-NEXT: [[R:%.*]] = shl nuw i8 1, [[S]] ; CHECK-NEXT: ret i8 [[R]] ; %s = sub i8 4, %x @@ -126,7 +126,7 @@ define i8 @shl_bad_sub_i8(i8 %x) { define i64 @shl_bad_sub_i64(i64 %x) { ; CHECK-LABEL: @shl_bad_sub_i64( ; CHECK-NEXT: [[S:%.*]] = sub i64 67, [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = shl i64 1, [[S]] +; CHECK-NEXT: [[R:%.*]] = shl nuw i64 1, [[S]] ; CHECK-NEXT: ret i64 [[R]] ; %s = sub i64 67, %x @@ -137,7 +137,7 @@ define i64 @shl_bad_sub_i64(i64 %x) { define <2 x i64> @shl_bad_sub_i64_vec(<2 x i64> %x) { ; CHECK-LABEL: @shl_bad_sub_i64_vec( ; CHECK-NEXT: [[S:%.*]] = sub <2 x i64> , [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = shl <2 x i64> , [[S]] +; CHECK-NEXT: [[R:%.*]] = shl nuw <2 x i64> , [[S]] ; CHECK-NEXT: ret <2 x i64> [[R]] ; %s = sub <2 x i64> , %x @@ -159,7 +159,7 @@ define <2 x i64> @bad_shl_sub_i64_vec(<2 x i64> %x) { define <3 x i64> @shl_sub_i64_vec_undef_bad(<3 x i64> %x) { ; CHECK-LABEL: @shl_sub_i64_vec_undef_bad( ; CHECK-NEXT: [[S:%.*]] = sub <3 x i64> , [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = shl <3 x i64> , [[S]] +; CHECK-NEXT: [[R:%.*]] = shl nuw <3 x i64> , [[S]] ; CHECK-NEXT: ret <3 x i64> [[R]] ; %s = sub <3 x i64> , %x @@ -170,7 +170,7 @@ define <3 x i64> @shl_sub_i64_vec_undef_bad(<3 x i64> %x) { define <3 x i64> @shl_sub_i64_vec_undef_bad2(<3 x i64> %x) { ; CHECK-LABEL: @shl_sub_i64_vec_undef_bad2( ; CHECK-NEXT: [[S:%.*]] = sub <3 x i64> , [[X:%.*]] -; CHECK-NEXT: [[R:%.*]] = shl <3 x i64> , [[S]] +; CHECK-NEXT: [[R:%.*]] = shl nuw <3 x i64> , [[S]] ; CHECK-NEXT: ret <3 x i64> [[R]] ; %s = sub <3 x i64> , %x diff --git a/llvm/test/Transforms/InstCombine/strchr-1.ll b/llvm/test/Transforms/InstCombine/strchr-1.ll index 180e034..191e0a1 100644 --- a/llvm/test/Transforms/InstCombine/strchr-1.ll +++ b/llvm/test/Transforms/InstCombine/strchr-1.ll @@ -87,7 +87,7 @@ define i1 @test_simplify7(i32 %C) { ; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[C:%.*]] to i16 ; CHECK-NEXT: [[TMP2:%.*]] = and i16 [[TMP1]], 255 ; CHECK-NEXT: [[MEMCHR_BOUNDS:%.*]] = icmp ult i16 [[TMP2]], 16 -; CHECK-NEXT: [[TMP3:%.*]] = shl i16 1, [[TMP2]] +; CHECK-NEXT: [[TMP3:%.*]] = shl nuw i16 1, [[TMP2]] ; CHECK-NEXT: [[TMP4:%.*]] = and i16 [[TMP3]], 9217 ; CHECK-NEXT: [[MEMCHR_BITS:%.*]] = icmp ne i16 [[TMP4]], 0 ; CHECK-NEXT: [[MEMCHR1:%.*]] = select i1 [[MEMCHR_BOUNDS]], i1 [[MEMCHR_BITS]], i1 false diff --git a/llvm/test/Transforms/InstCombine/sub-of-negatible-inseltpoison.ll b/llvm/test/Transforms/InstCombine/sub-of-negatible-inseltpoison.ll index 4437268..9dcdac2 100644 --- a/llvm/test/Transforms/InstCombine/sub-of-negatible-inseltpoison.ll +++ b/llvm/test/Transforms/InstCombine/sub-of-negatible-inseltpoison.ll @@ -145,7 +145,7 @@ define i8 @t7(i8 %x, i1 %y, i8 %z) { } define i8 @n8(i8 %x, i1 %y, i8 %z) { ; CHECK-LABEL: @n8( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[T1:%.*]] = select i1 [[Y:%.*]], i8 0, i8 [[T0]] ; CHECK-NEXT: [[T2:%.*]] = sub i8 [[X:%.*]], [[T1]] diff --git a/llvm/test/Transforms/InstCombine/sub-of-negatible.ll b/llvm/test/Transforms/InstCombine/sub-of-negatible.ll index 5cf345d..89b22f1 100644 --- a/llvm/test/Transforms/InstCombine/sub-of-negatible.ll +++ b/llvm/test/Transforms/InstCombine/sub-of-negatible.ll @@ -169,7 +169,7 @@ define i8 @t7(i8 %x, i1 %y, i8 %z) { } define i8 @n8(i8 %x, i1 %y, i8 %z) { ; CHECK-LABEL: @n8( -; CHECK-NEXT: [[T0:%.*]] = shl i8 1, [[Z:%.*]] +; CHECK-NEXT: [[T0:%.*]] = shl nuw i8 1, [[Z:%.*]] ; CHECK-NEXT: call void @use8(i8 [[T0]]) ; CHECK-NEXT: [[T1:%.*]] = select i1 [[Y:%.*]], i8 0, i8 [[T0]] ; CHECK-NEXT: [[T2:%.*]] = sub i8 [[X:%.*]], [[T1]] diff --git a/llvm/test/Transforms/InstCombine/xor.ll b/llvm/test/Transforms/InstCombine/xor.ll index fe2acf6..7ad8d79 100644 --- a/llvm/test/Transforms/InstCombine/xor.ll +++ b/llvm/test/Transforms/InstCombine/xor.ll @@ -1352,7 +1352,7 @@ define i32 @ctlz_pow2(i32 %x) { define <2 x i8> @cttz_pow2(<2 x i8> %x, <2 x i8> %y) { ; CHECK-LABEL: @cttz_pow2( -; CHECK-NEXT: [[S:%.*]] = shl <2 x i8> , [[X:%.*]] +; CHECK-NEXT: [[S:%.*]] = shl nuw <2 x i8> , [[X:%.*]] ; CHECK-NEXT: [[D:%.*]] = udiv exact <2 x i8> [[S]], [[Y:%.*]] ; CHECK-NEXT: [[R:%.*]] = call <2 x i8> @llvm.ctlz.v2i8(<2 x i8> [[D]], i1 true) ; CHECK-NEXT: ret <2 x i8> [[R]] diff --git a/llvm/test/Transforms/InstCombine/zext.ll b/llvm/test/Transforms/InstCombine/zext.ll index 25f59d5..43e50ed 100644 --- a/llvm/test/Transforms/InstCombine/zext.ll +++ b/llvm/test/Transforms/InstCombine/zext.ll @@ -236,7 +236,7 @@ define i32 @masked_bit_clear_commute(i32 %px, i32 %y) { define i32 @masked_bit_set_use1(i32 %x, i32 %y) { ; CHECK-LABEL: @masked_bit_set_use1( -; CHECK-NEXT: [[SH1:%.*]] = shl i32 1, [[Y:%.*]] +; CHECK-NEXT: [[SH1:%.*]] = shl nuw i32 1, [[Y:%.*]] ; CHECK-NEXT: call void @use32(i32 [[SH1]]) ; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[X:%.*]], [[Y]] ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 1 @@ -254,7 +254,7 @@ define i32 @masked_bit_set_use1(i32 %x, i32 %y) { define i32 @masked_bit_set_use2(i32 %x, i32 %y) { ; CHECK-LABEL: @masked_bit_set_use2( -; CHECK-NEXT: [[SH1:%.*]] = shl i32 1, [[Y:%.*]] +; CHECK-NEXT: [[SH1:%.*]] = shl nuw i32 1, [[Y:%.*]] ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SH1]], [[X:%.*]] ; CHECK-NEXT: call void @use32(i32 [[AND]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0 @@ -273,7 +273,7 @@ define i32 @masked_bit_set_use2(i32 %x, i32 %y) { define i32 @masked_bit_set_use3(i32 %x, i32 %y) { ; CHECK-LABEL: @masked_bit_set_use3( -; CHECK-NEXT: [[SH1:%.*]] = shl i32 1, [[Y:%.*]] +; CHECK-NEXT: [[SH1:%.*]] = shl nuw i32 1, [[Y:%.*]] ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SH1]], [[X:%.*]] ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0 ; CHECK-NEXT: call void @use1(i1 [[CMP]]) @@ -290,7 +290,7 @@ define i32 @masked_bit_set_use3(i32 %x, i32 %y) { define i32 @masked_bit_clear_use1(i32 %x, i32 %y) { ; CHECK-LABEL: @masked_bit_clear_use1( -; CHECK-NEXT: [[SH1:%.*]] = shl i32 1, [[Y:%.*]] +; CHECK-NEXT: [[SH1:%.*]] = shl nuw i32 1, [[Y:%.*]] ; CHECK-NEXT: call void @use32(i32 [[SH1]]) ; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[X:%.*]], -1 ; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 [[TMP1]], [[Y]] @@ -309,7 +309,7 @@ define i32 @masked_bit_clear_use1(i32 %x, i32 %y) { define i32 @masked_bit_clear_use2(i32 %x, i32 %y) { ; CHECK-LABEL: @masked_bit_clear_use2( -; CHECK-NEXT: [[SH1:%.*]] = shl i32 1, [[Y:%.*]] +; CHECK-NEXT: [[SH1:%.*]] = shl nuw i32 1, [[Y:%.*]] ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SH1]], [[X:%.*]] ; CHECK-NEXT: call void @use32(i32 [[AND]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0 @@ -328,7 +328,7 @@ define i32 @masked_bit_clear_use2(i32 %x, i32 %y) { define i32 @masked_bit_clear_use3(i32 %x, i32 %y) { ; CHECK-LABEL: @masked_bit_clear_use3( -; CHECK-NEXT: [[SH1:%.*]] = shl i32 1, [[Y:%.*]] +; CHECK-NEXT: [[SH1:%.*]] = shl nuw i32 1, [[Y:%.*]] ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SH1]], [[X:%.*]] ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[AND]], 0 ; CHECK-NEXT: call void @use1(i1 [[CMP]]) @@ -364,7 +364,7 @@ define i32 @masked_bits_set(i32 %x, i32 %y) { define i32 @div_bit_set(i32 %x, i32 %y) { ; CHECK-LABEL: @div_bit_set( -; CHECK-NEXT: [[SH1:%.*]] = shl i32 1, [[Y:%.*]] +; CHECK-NEXT: [[SH1:%.*]] = shl nuw i32 1, [[Y:%.*]] ; CHECK-NEXT: [[AND:%.*]] = sdiv i32 [[SH1]], [[X:%.*]] ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 0 ; CHECK-NEXT: [[R:%.*]] = zext i1 [[CMP]] to i32 @@ -381,7 +381,7 @@ define i32 @div_bit_set(i32 %x, i32 %y) { define i32 @masked_bit_set_nonzero_cmp(i32 %x, i32 %y) { ; CHECK-LABEL: @masked_bit_set_nonzero_cmp( -; CHECK-NEXT: [[SH1:%.*]] = shl i32 1, [[Y:%.*]] +; CHECK-NEXT: [[SH1:%.*]] = shl nuw i32 1, [[Y:%.*]] ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SH1]], [[X:%.*]] ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[AND]], 1 ; CHECK-NEXT: [[R:%.*]] = zext i1 [[CMP]] to i32 @@ -398,7 +398,7 @@ define i32 @masked_bit_set_nonzero_cmp(i32 %x, i32 %y) { define i32 @masked_bit_wrong_pred(i32 %x, i32 %y) { ; CHECK-LABEL: @masked_bit_wrong_pred( -; CHECK-NEXT: [[SH1:%.*]] = shl i32 1, [[Y:%.*]] +; CHECK-NEXT: [[SH1:%.*]] = shl nuw i32 1, [[Y:%.*]] ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SH1]], [[X:%.*]] ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[AND]], 0 ; CHECK-NEXT: [[R:%.*]] = zext i1 [[CMP]] to i32 @@ -413,7 +413,7 @@ define i32 @masked_bit_wrong_pred(i32 %x, i32 %y) { define i32 @zext_or_masked_bit_test(i32 %a, i32 %b, i32 %x) { ; CHECK-LABEL: @zext_or_masked_bit_test( -; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, [[B:%.*]] +; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, [[B:%.*]] ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL]], [[A:%.*]] ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[AND]], 0 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X:%.*]], [[B]] @@ -432,7 +432,7 @@ define i32 @zext_or_masked_bit_test(i32 %a, i32 %b, i32 %x) { define i32 @zext_or_masked_bit_test_uses(i32 %a, i32 %b, i32 %x) { ; CHECK-LABEL: @zext_or_masked_bit_test_uses( -; CHECK-NEXT: [[SHL:%.*]] = shl i32 1, [[B:%.*]] +; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, [[B:%.*]] ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHL]], [[A:%.*]] ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[AND]], 0 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X:%.*]], [[B]] -- cgit v1.1