From 63a5dc4aedaf8a4b26e536afb22612b4d69100bf Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Mon, 11 Mar 2024 15:35:05 +0000 Subject: [CodeGen] Do not pass MF into MachineRegisterInfo methods. NFC. (#84770) MachineRegisterInfo already knows the MF so there is no need to pass it in as an argument. --- llvm/include/llvm/CodeGen/MachineRegisterInfo.h | 9 ++++----- llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 2 +- llvm/lib/CodeGen/MachineOutliner.cpp | 2 +- llvm/lib/CodeGen/MachineRegisterInfo.cpp | 19 ++++++++----------- llvm/lib/CodeGen/RegAllocBase.cpp | 2 +- llvm/lib/CodeGen/RegAllocFast.cpp | 2 +- llvm/lib/CodeGen/RegAllocPBQP.cpp | 2 +- llvm/lib/CodeGen/TargetLoweringBase.cpp | 2 +- .../AArch64/AArch64LowerHomogeneousPrologEpilog.cpp | 2 +- llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp | 2 +- llvm/tools/llvm-exegesis/lib/Assembler.cpp | 2 +- llvm/tools/llvm-reduce/ReducerWorkItem.cpp | 2 +- 12 files changed, 22 insertions(+), 26 deletions(-) (limited to 'llvm') diff --git a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h index 257643c..3f0fc16 100644 --- a/llvm/include/llvm/CodeGen/MachineRegisterInfo.h +++ b/llvm/include/llvm/CodeGen/MachineRegisterInfo.h @@ -244,14 +244,13 @@ public: bool isUpdatedCSRsInitialized() const { return IsUpdatedCSRsInitialized; } /// Returns true if a register can be used as an argument to a function. - bool isArgumentRegister(const MachineFunction &MF, MCRegister Reg) const; + bool isArgumentRegister(MCRegister Reg) const; /// Returns true if a register is a fixed register. - bool isFixedRegister(const MachineFunction &MF, MCRegister Reg) const; + bool isFixedRegister(MCRegister Reg) const; /// Returns true if a register is a general purpose register. - bool isGeneralPurposeRegister(const MachineFunction &MF, - MCRegister Reg) const; + bool isGeneralPurposeRegister(MCRegister Reg) const; /// Disables the register from the list of CSRs. /// I.e. the register will not appear as part of the CSR mask. @@ -930,7 +929,7 @@ public: /// freezeReservedRegs - Called by the register allocator to freeze the set /// of reserved registers before allocation begins. - void freezeReservedRegs(const MachineFunction&); + void freezeReservedRegs(); /// reserveReg -- Mark a register as reserved so checks like isAllocatable /// will not suggest using it. This should not be used during the middle diff --git a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp index 54f55623..e09318a 100644 --- a/llvm/lib/CodeGen/MIRParser/MIRParser.cpp +++ b/llvm/lib/CodeGen/MIRParser/MIRParser.cpp @@ -574,7 +574,7 @@ MIRParserImpl::initializeMachineFunction(const yaml::MachineFunction &YamlMF, // FIXME: This is a temporary workaround until the reserved registers can be // serialized. MachineRegisterInfo &MRI = MF.getRegInfo(); - MRI.freezeReservedRegs(MF); + MRI.freezeReservedRegs(); computeFunctionProperties(MF); diff --git a/llvm/lib/CodeGen/MachineOutliner.cpp b/llvm/lib/CodeGen/MachineOutliner.cpp index b8d3b2e..dc2f5ef 100644 --- a/llvm/lib/CodeGen/MachineOutliner.cpp +++ b/llvm/lib/CodeGen/MachineOutliner.cpp @@ -759,7 +759,7 @@ MachineFunction *MachineOutliner::createOutlinedFunction( MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs); MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs); MF.getProperties().set(MachineFunctionProperties::Property::TracksLiveness); - MF.getRegInfo().freezeReservedRegs(MF); + MF.getRegInfo().freezeReservedRegs(); // Compute live-in set for outlined fn const MachineRegisterInfo &MRI = MF.getRegInfo(); diff --git a/llvm/lib/CodeGen/MachineRegisterInfo.cpp b/llvm/lib/CodeGen/MachineRegisterInfo.cpp index e88487f..55d7c83 100644 --- a/llvm/lib/CodeGen/MachineRegisterInfo.cpp +++ b/llvm/lib/CodeGen/MachineRegisterInfo.cpp @@ -517,8 +517,8 @@ LLVM_DUMP_METHOD void MachineRegisterInfo::dumpUses(Register Reg) const { } #endif -void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) { - ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF); +void MachineRegisterInfo::freezeReservedRegs() { + ReservedRegs = getTargetRegisterInfo()->getReservedRegs(*MF); assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() && "Invalid ReservedRegs vector from target"); } @@ -660,17 +660,14 @@ bool MachineRegisterInfo::isReservedRegUnit(unsigned Unit) const { return false; } -bool MachineRegisterInfo::isArgumentRegister(const MachineFunction &MF, - MCRegister Reg) const { - return getTargetRegisterInfo()->isArgumentRegister(MF, Reg); +bool MachineRegisterInfo::isArgumentRegister(MCRegister Reg) const { + return getTargetRegisterInfo()->isArgumentRegister(*MF, Reg); } -bool MachineRegisterInfo::isFixedRegister(const MachineFunction &MF, - MCRegister Reg) const { - return getTargetRegisterInfo()->isFixedRegister(MF, Reg); +bool MachineRegisterInfo::isFixedRegister(MCRegister Reg) const { + return getTargetRegisterInfo()->isFixedRegister(*MF, Reg); } -bool MachineRegisterInfo::isGeneralPurposeRegister(const MachineFunction &MF, - MCRegister Reg) const { - return getTargetRegisterInfo()->isGeneralPurposeRegister(MF, Reg); +bool MachineRegisterInfo::isGeneralPurposeRegister(MCRegister Reg) const { + return getTargetRegisterInfo()->isGeneralPurposeRegister(*MF, Reg); } diff --git a/llvm/lib/CodeGen/RegAllocBase.cpp b/llvm/lib/CodeGen/RegAllocBase.cpp index 900f0e9..d0dec37 100644 --- a/llvm/lib/CodeGen/RegAllocBase.cpp +++ b/llvm/lib/CodeGen/RegAllocBase.cpp @@ -61,7 +61,7 @@ void RegAllocBase::init(VirtRegMap &vrm, LiveIntervals &lis, VRM = &vrm; LIS = &lis; Matrix = &mat; - MRI->freezeReservedRegs(vrm.getMachineFunction()); + MRI->freezeReservedRegs(); RegClassInfo.runOnMachineFunction(vrm.getMachineFunction()); } diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp index e81d479..6740e1f 100644 --- a/llvm/lib/CodeGen/RegAllocFast.cpp +++ b/llvm/lib/CodeGen/RegAllocFast.cpp @@ -1740,7 +1740,7 @@ bool RegAllocFast::runOnMachineFunction(MachineFunction &MF) { TRI = STI.getRegisterInfo(); TII = STI.getInstrInfo(); MFI = &MF.getFrameInfo(); - MRI->freezeReservedRegs(MF); + MRI->freezeReservedRegs(); RegClassInfo.runOnMachineFunction(MF); unsigned NumRegUnits = TRI->getNumRegUnits(); UsedInInstr.clear(); diff --git a/llvm/lib/CodeGen/RegAllocPBQP.cpp b/llvm/lib/CodeGen/RegAllocPBQP.cpp index b8ee5dc..aea92788 100644 --- a/llvm/lib/CodeGen/RegAllocPBQP.cpp +++ b/llvm/lib/CodeGen/RegAllocPBQP.cpp @@ -809,7 +809,7 @@ bool RegAllocPBQP::runOnMachineFunction(MachineFunction &MF) { std::unique_ptr VRegSpiller( createInlineSpiller(*this, MF, VRM, DefaultVRAI)); - MF.getRegInfo().freezeReservedRegs(MF); + MF.getRegInfo().freezeReservedRegs(); LLVM_DEBUG(dbgs() << "PBQP Register Allocating for " << MF.getName() << "\n"); diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp index a2aeb66..8ac55ee 100644 --- a/llvm/lib/CodeGen/TargetLoweringBase.cpp +++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp @@ -2336,7 +2336,7 @@ bool TargetLoweringBase::isLoadBitCastBeneficial( } void TargetLoweringBase::finalizeLowering(MachineFunction &MF) const { - MF.getRegInfo().freezeReservedRegs(MF); + MF.getRegInfo().freezeReservedRegs(); } MachineMemOperand::Flags TargetLoweringBase::getLoadMemOperandFlags( diff --git a/llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp b/llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp index 4afc678..d21aa59 100644 --- a/llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp +++ b/llvm/lib/Target/AArch64/AArch64LowerHomogeneousPrologEpilog.cpp @@ -183,7 +183,7 @@ static MachineFunction &createFrameHelperMachineFunction(Module *M, MF.getProperties().reset(MachineFunctionProperties::Property::TracksLiveness); MF.getProperties().reset(MachineFunctionProperties::Property::IsSSA); MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs); - MF.getRegInfo().freezeReservedRegs(MF); + MF.getRegInfo().freezeReservedRegs(); // Create entry block. BasicBlock *EntryBB = BasicBlock::Create(C, "entry", F); diff --git a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp index 0c57110..398f870 100644 --- a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp +++ b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp @@ -156,7 +156,7 @@ void SIPreAllocateWWMRegs::rewriteRegs(MachineFunction &MF) { RegsToRewrite.clear(); // Update the set of reserved registers to include WWM ones. - MRI->freezeReservedRegs(MF); + MRI->freezeReservedRegs(); } #ifndef NDEBUG diff --git a/llvm/tools/llvm-exegesis/lib/Assembler.cpp b/llvm/tools/llvm-exegesis/lib/Assembler.cpp index 3aad913..92ab3a9 100644 --- a/llvm/tools/llvm-exegesis/lib/Assembler.cpp +++ b/llvm/tools/llvm-exegesis/lib/Assembler.cpp @@ -305,7 +305,7 @@ Error assembleToStream(const ExegesisTarget &ET, // prologue/epilogue pass needs the reserved registers to be frozen, this // is usually done by the SelectionDAGISel pass. - MF.getRegInfo().freezeReservedRegs(MF); + MF.getRegInfo().freezeReservedRegs(); // We create the pass manager, run the passes to populate AsmBuffer. MCContext &MCContext = MMIWP->getMMI().getContext(); diff --git a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp index 3532167..78e6f72 100644 --- a/llvm/tools/llvm-reduce/ReducerWorkItem.cpp +++ b/llvm/tools/llvm-reduce/ReducerWorkItem.cpp @@ -414,7 +414,7 @@ static std::unique_ptr cloneMF(MachineFunction *SrcMF, if (!DstMF->cloneInfoFrom(*SrcMF, Src2DstMBB)) report_fatal_error("target does not implement MachineFunctionInfo cloning"); - DstMRI->freezeReservedRegs(*DstMF); + DstMRI->freezeReservedRegs(); DstMF->verify(nullptr, "", /*AbortOnError=*/true); return DstMF; -- cgit v1.1