From fbb0f2dba040bbdd5de5e59201c1a6fb9be3e06d Mon Sep 17 00:00:00 2001 From: Lei Huang Date: Tue, 2 Sep 2025 17:14:09 -0400 Subject: [PowerPC] Implement vector uncompress instructions (#150702) Implement the set of vector uncompress instructions: * vucmprhh * vucmprlh * vucmprhn * vucmprln * vucmprhb * vucmprlb --- .../PowerPC/ppc-encoding-ISAFuture.txt | 18 ++++++++++++++++ .../PowerPC/ppc64le-encoding-ISAFuture.txt | 18 ++++++++++++++++ llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s | 24 ++++++++++++++++++++++ 3 files changed, 60 insertions(+) (limited to 'llvm/test') diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt index 6adaa5c..da3601b 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt @@ -213,3 +213,21 @@ #CHECK: vupkint8tofp32 3, 5, 2 0x10,0x6e,0x29,0x83 + +#CHECK: vucmprhn 0, 2, 3 +0x10,0x02,0x18,0x03 + +#CHECK: vucmprln 3, 5, 6 +0x10,0x65,0x30,0x43 + +#CHECK: vucmprhb 1, 3, 6 +0x10,0x23,0x30,0x83 + +#CHECK: vucmprlb 2, 4, 5 +0x10,0x44,0x28,0xC3 + +#CHECK: vucmprlh 2, 4, 5 +0x10,0x44,0x29,0x43 + +#CHECK: vucmprhh 1, 3, 6 +0x10,0x23,0x31,0x03 diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt index 84f9bc8..66d0504 100644 --- a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt +++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt @@ -207,3 +207,21 @@ #CHECK: vupkint8tofp32 3, 5, 2 0x83,0x29,0x6e,0x10 + +#CHECK: vucmprhn 0, 2, 3 +0x03,0x18,0x02,0x10 + +#CHECK: vucmprln 3, 5, 6 +0x43,0x30,0x65,0x10 + +#CHECK: vucmprhb 1, 3, 6 +0x83,0x30,0x23,0x10 + +#CHECK: vucmprlb 2, 4, 5 +0xC3,0x28,0x44,0x10 + +#CHECK: vucmprlh 2, 4, 5 +0x43,0x29,0x44,0x10 + +#CHECK: vucmprhh 1, 3, 6 +0x03,0x31,0x23,0x10 diff --git a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s index 8316bbd..6ae7bd7 100644 --- a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s +++ b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s @@ -306,3 +306,27 @@ vupkint8tofp32 3, 5, 2 #CHECK-BE: vupkint8tofp32 3, 5, 2 # encoding: [0x10,0x6e,0x29,0x83] #CHECK-LE: vupkint8tofp32 3, 5, 2 # encoding: [0x83,0x29,0x6e,0x10] + + vucmprhn 0, 2, 3 +#CHECK-BE: vucmprhn 0, 2, 3 # encoding: [0x10,0x02,0x18,0x03] +#CHECK-LE: vucmprhn 0, 2, 3 # encoding: [0x03,0x18,0x02,0x10] + + vucmprln 3, 5, 6 +#CHECK-BE: vucmprln 3, 5, 6 # encoding: [0x10,0x65,0x30,0x43] +#CHECK-LE: vucmprln 3, 5, 6 # encoding: [0x43,0x30,0x65,0x10] + + vucmprhb 1, 3, 6 +#CHECK-BE: vucmprhb 1, 3, 6 # encoding: [0x10,0x23,0x30,0x83] +#CHECK-LE: vucmprhb 1, 3, 6 # encoding: [0x83,0x30,0x23,0x10] + + vucmprlb 2, 4, 5 +#CHECK-BE: vucmprlb 2, 4, 5 # encoding: [0x10,0x44,0x28,0xc3] +#CHECK-LE: vucmprlb 2, 4, 5 # encoding: [0xc3,0x28,0x44,0x10] + + vucmprlh 2, 4, 5 +#CHECK-BE: vucmprlh 2, 4, 5 # encoding: [0x10,0x44,0x29,0x43] +#CHECK-LE: vucmprlh 2, 4, 5 # encoding: [0x43,0x29,0x44,0x10] + + vucmprhh 1, 3, 6 +#CHECK-BE: vucmprhh 1, 3, 6 # encoding: [0x10,0x23,0x31,0x03] +#CHECK-LE: vucmprhh 1, 3, 6 # encoding: [0x03,0x31,0x23,0x10] -- cgit v1.1