From 59720b422abfc090aadf246eb3c7fc583aeb2693 Mon Sep 17 00:00:00 2001
From: Diana Picus <diana.picus@linaro.org>
Date: Wed, 12 Dec 2018 10:32:15 +0000
Subject: [ARM GlobalISel] Select load/store for Thumb2

Unfortunately we can't use TableGen for this because it doesn't yet
support predicates on the source pattern root. Therefore, add a bit of
handwritten code to the instruction selector to handle the most basic
cases.

Also mark them as legal and extract their legalizer test cases to a new
test file.

llvm-svn: 348920
---
 llvm/lib/Target/ARM/ARMInstructionSelector.cpp | 18 ++++++++++++++++--
 llvm/lib/Target/ARM/ARMLegalizerInfo.cpp       | 22 ++++++++++++++++++----
 2 files changed, 34 insertions(+), 6 deletions(-)

(limited to 'llvm/lib')

diff --git a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
index 6692a4d..2d5c990 100644
--- a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
+++ b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
@@ -248,10 +248,23 @@ static unsigned selectSimpleExtOpc(unsigned Opc, unsigned Size) {
 /// bits, the value will be zero extended. Returns the original opcode if it
 /// doesn't know how to select a better one.
 static unsigned selectLoadStoreOpCode(unsigned Opc, unsigned RegBank,
-                                      unsigned Size) {
+                                      unsigned Size, bool isThumb) {
   bool isStore = Opc == TargetOpcode::G_STORE;
 
   if (RegBank == ARM::GPRRegBankID) {
+    if (isThumb)
+      switch (Size) {
+      case 1:
+      case 8:
+        return isStore ? ARM::t2STRBi12 : ARM::t2LDRBi12;
+      case 16:
+        return isStore ? ARM::t2STRHi12 : ARM::t2LDRHi12;
+      case 32:
+        return isStore ? ARM::t2STRi12 : ARM::t2LDRi12;
+      default:
+        return Opc;
+      }
+
     switch (Size) {
     case 1:
     case 8:
@@ -901,7 +914,8 @@ bool ARMInstructionSelector::select(MachineInstr &I,
     assert((ValSize != 64 || STI.hasVFP2()) &&
            "Don't know how to load/store 64-bit value without VFP");
 
-    const auto NewOpc = selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize);
+    const auto NewOpc =
+        selectLoadStoreOpCode(I.getOpcode(), RegBank, ValSize, STI.isThumb());
     if (NewOpc == G_LOAD || NewOpc == G_STORE)
       return false;
 
diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
index 0455f668..2edeeac 100644
--- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
@@ -75,6 +75,24 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
   const LLT s32 = LLT::scalar(32);
   const LLT s64 = LLT::scalar(64);
 
+  if (ST.isThumb1Only()) {
+    // Thumb1 is not supported yet.
+    computeTables();
+    verify(*ST.getInstrInfo());
+    return;
+  }
+
+  // We're keeping these builders around because we'll want to add support for
+  // floating point to them.
+  auto &LoadStoreBuilder =
+      getActionDefinitionsBuilder({G_LOAD, G_STORE})
+          .legalForTypesWithMemSize({
+              {s1, p0, 8},
+              {s8, p0, 8},
+              {s16, p0, 16},
+              {s32, p0, 32},
+              {p0, p0, 32}});
+
   if (ST.isThumb()) {
     // FIXME: merge with the code for non-Thumb.
     computeTables();
@@ -149,10 +167,6 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) {
 
   // We're keeping these builders around because we'll want to add support for
   // floating point to them.
-  auto &LoadStoreBuilder =
-      getActionDefinitionsBuilder({G_LOAD, G_STORE})
-          .legalForCartesianProduct({s1, s8, s16, s32, p0}, {p0});
-
   auto &PhiBuilder =
       getActionDefinitionsBuilder(G_PHI).legalFor({s32, p0}).minScalar(0, s32);
 
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