From 919c547130cfd1cd75ccf148cbf2334b27b2f37f Mon Sep 17 00:00:00 2001 From: Shengchen Kan Date: Thu, 20 Jun 2024 17:31:18 +0800 Subject: [X86] Fix indention in X86InstrArithmetic.td, NFCI --- llvm/lib/Target/X86/X86InstrArithmetic.td | 386 +++++++++++++++--------------- 1 file changed, 187 insertions(+), 199 deletions(-) (limited to 'llvm/lib/Target') diff --git a/llvm/lib/Target/X86/X86InstrArithmetic.td b/llvm/lib/Target/X86/X86InstrArithmetic.td index c45ec89..552a4a3 100644 --- a/llvm/lib/Target/X86/X86InstrArithmetic.td +++ b/llvm/lib/Target/X86/X86InstrArithmetic.td @@ -14,34 +14,34 @@ //===----------------------------------------------------------------------===// // LEA - Load Effective Address let SchedRW = [WriteLEA] in { -let hasSideEffects = 0 in -def LEA16r : I<0x8D, MRMSrcMem, - (outs GR16:$dst), (ins anymem:$src), - "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize16; -let isReMaterializable = 1 in -def LEA32r : I<0x8D, MRMSrcMem, - (outs GR32:$dst), (ins anymem:$src), - "lea{l}\t{$src|$dst}, {$dst|$src}", - [(set GR32:$dst, lea32addr:$src)]>, - OpSize32, Requires<[Not64BitMode]>; - -def LEA64_32r : I<0x8D, MRMSrcMem, - (outs GR32:$dst), (ins lea64_32mem:$src), - "lea{l}\t{$src|$dst}, {$dst|$src}", - [(set GR32:$dst, lea64_32addr:$src)]>, - OpSize32, Requires<[In64BitMode]>; - -let isReMaterializable = 1 in -def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src), - "lea{q}\t{$src|$dst}, {$dst|$src}", - [(set GR64:$dst, lea64addr:$src)]>; + let hasSideEffects = 0 in + def LEA16r : I<0x8D, MRMSrcMem, + (outs GR16:$dst), (ins anymem:$src), + "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize16; + let isReMaterializable = 1 in + def LEA32r : I<0x8D, MRMSrcMem, + (outs GR32:$dst), (ins anymem:$src), + "lea{l}\t{$src|$dst}, {$dst|$src}", + [(set GR32:$dst, lea32addr:$src)]>, + OpSize32, Requires<[Not64BitMode]>; + + def LEA64_32r : I<0x8D, MRMSrcMem, + (outs GR32:$dst), (ins lea64_32mem:$src), + "lea{l}\t{$src|$dst}, {$dst|$src}", + [(set GR32:$dst, lea64_32addr:$src)]>, + OpSize32, Requires<[In64BitMode]>; + + let isReMaterializable = 1 in + def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src), + "lea{q}\t{$src|$dst}, {$dst|$src}", + [(set GR64:$dst, lea64addr:$src)]>; } // SchedRW // Pseudo instruction for lea that prevent optimizer from eliminating // the instruction. let SchedRW = [WriteLEA], isPseudo = true, hasSideEffects = 1 in { -def PLEA32r : PseudoI<(outs GR32:$dst), (ins anymem:$src), []>; -def PLEA64r : PseudoI<(outs GR64:$dst), (ins anymem:$src), []>; + def PLEA32r : PseudoI<(outs GR32:$dst), (ins anymem:$src), []>; + def PLEA64r : PseudoI<(outs GR64:$dst), (ins anymem:$src), []>; } //===----------------------------------------------------------------------===// @@ -655,107 +655,107 @@ multiclass ArithBinOp_RF BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4, } } - def 8rr_REV : BinOpRR_RF_Rev; - def 16rr_REV : BinOpRR_RF_Rev, OpSize16; - def 32rr_REV : BinOpRR_RF_Rev, OpSize32; - def 64rr_REV : BinOpRR_RF_Rev; - let Predicates = [In64BitMode] in { - def 8rr_EVEX_REV : BinOpRR_RF_Rev, PL; - def 16rr_EVEX_REV : BinOpRR_RF_Rev, PL, PD; - def 32rr_EVEX_REV : BinOpRR_RF_Rev, PL; - def 64rr_EVEX_REV : BinOpRR_RF_Rev, PL; - def 8rr_ND_REV : BinOpRR_RF_Rev; - def 16rr_ND_REV : BinOpRR_RF_Rev, PD; - def 32rr_ND_REV : BinOpRR_RF_Rev; - def 64rr_ND_REV : BinOpRR_RF_Rev; - def 8rr_NF_REV : BinOpRR_R_Rev, NF; - def 16rr_NF_REV : BinOpRR_R_Rev, NF, PD; - def 32rr_NF_REV : BinOpRR_R_Rev, NF; - def 64rr_NF_REV : BinOpRR_R_Rev, NF; - def 8rr_NF_ND_REV : BinOpRR_R_Rev, EVEX_NF; - def 16rr_NF_ND_REV : BinOpRR_R_Rev, EVEX_NF, PD; - def 32rr_NF_ND_REV : BinOpRR_R_Rev, EVEX_NF; - def 64rr_NF_ND_REV : BinOpRR_R_Rev, EVEX_NF; - } + def 8rr_REV : BinOpRR_RF_Rev; + def 16rr_REV : BinOpRR_RF_Rev, OpSize16; + def 32rr_REV : BinOpRR_RF_Rev, OpSize32; + def 64rr_REV : BinOpRR_RF_Rev; + let Predicates = [In64BitMode] in { + def 8rr_EVEX_REV : BinOpRR_RF_Rev, PL; + def 16rr_EVEX_REV : BinOpRR_RF_Rev, PL, PD; + def 32rr_EVEX_REV : BinOpRR_RF_Rev, PL; + def 64rr_EVEX_REV : BinOpRR_RF_Rev, PL; + def 8rr_ND_REV : BinOpRR_RF_Rev; + def 16rr_ND_REV : BinOpRR_RF_Rev, PD; + def 32rr_ND_REV : BinOpRR_RF_Rev; + def 64rr_ND_REV : BinOpRR_RF_Rev; + def 8rr_NF_REV : BinOpRR_R_Rev, NF; + def 16rr_NF_REV : BinOpRR_R_Rev, NF, PD; + def 32rr_NF_REV : BinOpRR_R_Rev, NF; + def 64rr_NF_REV : BinOpRR_R_Rev, NF; + def 8rr_NF_ND_REV : BinOpRR_R_Rev, EVEX_NF; + def 16rr_NF_ND_REV : BinOpRR_R_Rev, EVEX_NF, PD; + def 32rr_NF_ND_REV : BinOpRR_R_Rev, EVEX_NF; + def 64rr_NF_ND_REV : BinOpRR_R_Rev, EVEX_NF; + } + let Predicates = [NoNDD] in { + def 8rm : BinOpRM_RF; + def 16rm : BinOpRM_RF, OpSize16; + def 32rm : BinOpRM_RF, OpSize32; + def 64rm : BinOpRM_RF; + } + let Predicates = [HasNDD, In64BitMode] in { + def 8rm_ND : BinOpRM_RF; + def 16rm_ND : BinOpRM_RF, PD; + def 32rm_ND : BinOpRM_RF; + def 64rm_ND : BinOpRM_RF; + def 8rm_NF_ND : BinOpRM_R, EVEX_NF; + def 16rm_NF_ND : BinOpRM_R, EVEX_NF, PD; + def 32rm_NF_ND : BinOpRM_R, EVEX_NF; + def 64rm_NF_ND : BinOpRM_R, EVEX_NF; + } + let Predicates = [In64BitMode] in { + def 8rm_NF : BinOpRM_R, NF; + def 16rm_NF : BinOpRM_R, NF, PD; + def 32rm_NF : BinOpRM_R, NF; + def 64rm_NF : BinOpRM_R, NF; + def 8rm_EVEX : BinOpRM_RF, PL; + def 16rm_EVEX : BinOpRM_RF, PL, PD; + def 32rm_EVEX : BinOpRM_RF, PL; + def 64rm_EVEX : BinOpRM_RF, PL; + } + + let isConvertibleToThreeAddress = ConvertibleToThreeAddress in { let Predicates = [NoNDD] in { - def 8rm : BinOpRM_RF; - def 16rm : BinOpRM_RF, OpSize16; - def 32rm : BinOpRM_RF, OpSize32; - def 64rm : BinOpRM_RF; + // NOTE: These are order specific, we want the ri8 forms to be listed + // first so that they are slightly preferred to the ri forms. + def 16ri8 : BinOpRI8_RF<0x83, mnemonic, Xi16, RegMRM>, OpSize16; + def 32ri8 : BinOpRI8_RF<0x83, mnemonic, Xi32, RegMRM>, OpSize32; + def 64ri8 : BinOpRI8_RF<0x83, mnemonic, Xi64, RegMRM>; + def 8ri : BinOpRI_RF<0x80, mnemonic, Xi8 , opnodeflag, RegMRM>; + def 16ri : BinOpRI_RF<0x81, mnemonic, Xi16, opnodeflag, RegMRM>, OpSize16; + def 32ri : BinOpRI_RF<0x81, mnemonic, Xi32, opnodeflag, RegMRM>, OpSize32; + def 64ri32: BinOpRI_RF<0x81, mnemonic, Xi64, opnodeflag, RegMRM>; } let Predicates = [HasNDD, In64BitMode] in { - def 8rm_ND : BinOpRM_RF; - def 16rm_ND : BinOpRM_RF, PD; - def 32rm_ND : BinOpRM_RF; - def 64rm_ND : BinOpRM_RF; - def 8rm_NF_ND : BinOpRM_R, EVEX_NF; - def 16rm_NF_ND : BinOpRM_R, EVEX_NF, PD; - def 32rm_NF_ND : BinOpRM_R, EVEX_NF; - def 64rm_NF_ND : BinOpRM_R, EVEX_NF; + def 16ri8_ND : BinOpRI8_RF<0x83, mnemonic, Xi16, RegMRM, 1>, PD; + def 32ri8_ND : BinOpRI8_RF<0x83, mnemonic, Xi32, RegMRM, 1>; + def 64ri8_ND : BinOpRI8_RF<0x83, mnemonic, Xi64, RegMRM, 1>; + def 8ri_ND : BinOpRI_RF<0x80, mnemonic, Xi8 , opnodeflag, RegMRM, 1>; + def 16ri_ND : BinOpRI_RF<0x81, mnemonic, Xi16, opnodeflag, RegMRM, 1>, PD; + def 32ri_ND : BinOpRI_RF<0x81, mnemonic, Xi32, opnodeflag, RegMRM, 1>; + def 64ri32_ND: BinOpRI_RF<0x81, mnemonic, Xi64, opnodeflag, RegMRM, 1>; + def 16ri8_NF_ND : BinOpRI8_R<0x83, mnemonic, Xi16, RegMRM, 1>, EVEX_NF, PD; + def 32ri8_NF_ND : BinOpRI8_R<0x83, mnemonic, Xi32, RegMRM, 1>, EVEX_NF; + def 64ri8_NF_ND : BinOpRI8_R<0x83, mnemonic, Xi64, RegMRM, 1>, EVEX_NF; + def 8ri_NF_ND : BinOpRI_R<0x80, mnemonic, Xi8, RegMRM, 1>, EVEX_NF; + def 16ri_NF_ND : BinOpRI_R<0x81, mnemonic, Xi16, RegMRM, 1>, EVEX_NF, PD; + def 32ri_NF_ND : BinOpRI_R<0x81, mnemonic, Xi32, RegMRM, 1>, EVEX_NF; + def 64ri32_NF_ND : BinOpRI_R<0x81, mnemonic, Xi64, RegMRM, 1>, EVEX_NF; } let Predicates = [In64BitMode] in { - def 8rm_NF : BinOpRM_R, NF; - def 16rm_NF : BinOpRM_R, NF, PD; - def 32rm_NF : BinOpRM_R, NF; - def 64rm_NF : BinOpRM_R, NF; - def 8rm_EVEX : BinOpRM_RF, PL; - def 16rm_EVEX : BinOpRM_RF, PL, PD; - def 32rm_EVEX : BinOpRM_RF, PL; - def 64rm_EVEX : BinOpRM_RF, PL; - } - - let isConvertibleToThreeAddress = ConvertibleToThreeAddress in { - let Predicates = [NoNDD] in { - // NOTE: These are order specific, we want the ri8 forms to be listed - // first so that they are slightly preferred to the ri forms. - def 16ri8 : BinOpRI8_RF<0x83, mnemonic, Xi16, RegMRM>, OpSize16; - def 32ri8 : BinOpRI8_RF<0x83, mnemonic, Xi32, RegMRM>, OpSize32; - def 64ri8 : BinOpRI8_RF<0x83, mnemonic, Xi64, RegMRM>; - def 8ri : BinOpRI_RF<0x80, mnemonic, Xi8 , opnodeflag, RegMRM>; - def 16ri : BinOpRI_RF<0x81, mnemonic, Xi16, opnodeflag, RegMRM>, OpSize16; - def 32ri : BinOpRI_RF<0x81, mnemonic, Xi32, opnodeflag, RegMRM>, OpSize32; - def 64ri32: BinOpRI_RF<0x81, mnemonic, Xi64, opnodeflag, RegMRM>; - } - let Predicates = [HasNDD, In64BitMode] in { - def 16ri8_ND : BinOpRI8_RF<0x83, mnemonic, Xi16, RegMRM, 1>, PD; - def 32ri8_ND : BinOpRI8_RF<0x83, mnemonic, Xi32, RegMRM, 1>; - def 64ri8_ND : BinOpRI8_RF<0x83, mnemonic, Xi64, RegMRM, 1>; - def 8ri_ND : BinOpRI_RF<0x80, mnemonic, Xi8 , opnodeflag, RegMRM, 1>; - def 16ri_ND : BinOpRI_RF<0x81, mnemonic, Xi16, opnodeflag, RegMRM, 1>, PD; - def 32ri_ND : BinOpRI_RF<0x81, mnemonic, Xi32, opnodeflag, RegMRM, 1>; - def 64ri32_ND: BinOpRI_RF<0x81, mnemonic, Xi64, opnodeflag, RegMRM, 1>; - def 16ri8_NF_ND : BinOpRI8_R<0x83, mnemonic, Xi16, RegMRM, 1>, EVEX_NF, PD; - def 32ri8_NF_ND : BinOpRI8_R<0x83, mnemonic, Xi32, RegMRM, 1>, EVEX_NF; - def 64ri8_NF_ND : BinOpRI8_R<0x83, mnemonic, Xi64, RegMRM, 1>, EVEX_NF; - def 8ri_NF_ND : BinOpRI_R<0x80, mnemonic, Xi8, RegMRM, 1>, EVEX_NF; - def 16ri_NF_ND : BinOpRI_R<0x81, mnemonic, Xi16, RegMRM, 1>, EVEX_NF, PD; - def 32ri_NF_ND : BinOpRI_R<0x81, mnemonic, Xi32, RegMRM, 1>, EVEX_NF; - def 64ri32_NF_ND : BinOpRI_R<0x81, mnemonic, Xi64, RegMRM, 1>, EVEX_NF; - } - let Predicates = [In64BitMode] in { - def 16ri8_NF : BinOpRI8_R<0x83, mnemonic, Xi16, RegMRM>, NF, PD; - def 32ri8_NF : BinOpRI8_R<0x83, mnemonic, Xi32, RegMRM>, NF; - def 64ri8_NF : BinOpRI8_R<0x83, mnemonic, Xi64, RegMRM>, NF; - def 8ri_NF : BinOpRI_R<0x80, mnemonic, Xi8, RegMRM>, NF; - def 16ri_NF : BinOpRI_R<0x81, mnemonic, Xi16, RegMRM>, NF, PD; - def 32ri_NF : BinOpRI_R<0x81, mnemonic, Xi32, RegMRM>, NF; - def 64ri32_NF : BinOpRI_R<0x81, mnemonic, Xi64, RegMRM>, NF; - def 16ri8_EVEX : BinOpRI8_RF<0x83, mnemonic, Xi16, RegMRM>, PL, PD; - def 32ri8_EVEX : BinOpRI8_RF<0x83, mnemonic, Xi32, RegMRM>, PL; - def 64ri8_EVEX : BinOpRI8_RF<0x83, mnemonic, Xi64, RegMRM>, PL; - def 8ri_EVEX : BinOpRI_RF<0x80, mnemonic, Xi8 , null_frag, RegMRM>, PL; - def 16ri_EVEX : BinOpRI_RF<0x81, mnemonic, Xi16, null_frag, RegMRM>, PL, PD; - def 32ri_EVEX : BinOpRI_RF<0x81, mnemonic, Xi32, null_frag, RegMRM>, PL; - def 64ri32_EVEX: BinOpRI_RF<0x81, mnemonic, Xi64, null_frag, RegMRM>, PL; - } + def 16ri8_NF : BinOpRI8_R<0x83, mnemonic, Xi16, RegMRM>, NF, PD; + def 32ri8_NF : BinOpRI8_R<0x83, mnemonic, Xi32, RegMRM>, NF; + def 64ri8_NF : BinOpRI8_R<0x83, mnemonic, Xi64, RegMRM>, NF; + def 8ri_NF : BinOpRI_R<0x80, mnemonic, Xi8, RegMRM>, NF; + def 16ri_NF : BinOpRI_R<0x81, mnemonic, Xi16, RegMRM>, NF, PD; + def 32ri_NF : BinOpRI_R<0x81, mnemonic, Xi32, RegMRM>, NF; + def 64ri32_NF : BinOpRI_R<0x81, mnemonic, Xi64, RegMRM>, NF; + def 16ri8_EVEX : BinOpRI8_RF<0x83, mnemonic, Xi16, RegMRM>, PL, PD; + def 32ri8_EVEX : BinOpRI8_RF<0x83, mnemonic, Xi32, RegMRM>, PL; + def 64ri8_EVEX : BinOpRI8_RF<0x83, mnemonic, Xi64, RegMRM>, PL; + def 8ri_EVEX : BinOpRI_RF<0x80, mnemonic, Xi8 , null_frag, RegMRM>, PL; + def 16ri_EVEX : BinOpRI_RF<0x81, mnemonic, Xi16, null_frag, RegMRM>, PL, PD; + def 32ri_EVEX : BinOpRI_RF<0x81, mnemonic, Xi32, null_frag, RegMRM>, PL; + def 64ri32_EVEX: BinOpRI_RF<0x81, mnemonic, Xi64, null_frag, RegMRM>, PL; } + } - def 8mr : BinOpMR_MF; - def 16mr : BinOpMR_MF, OpSize16; - def 32mr : BinOpMR_MF, OpSize32; - def 64mr : BinOpMR_MF; - let Predicates = [HasNDD, In64BitMode] in { + def 8mr : BinOpMR_MF; + def 16mr : BinOpMR_MF, OpSize16; + def 32mr : BinOpMR_MF, OpSize32; + def 64mr : BinOpMR_MF; + let Predicates = [HasNDD, In64BitMode] in { def 8mr_ND : BinOpMR_RF; def 16mr_ND : BinOpMR_RF, PD; def 32mr_ND : BinOpMR_RF; @@ -823,18 +823,14 @@ multiclass ArithBinOp_RF BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4, // These are for the disassembler since 0x82 opcode behaves like 0x80, but // not in 64-bit mode. let Predicates = [Not64BitMode] in { - def 8ri8 : BinOpRI8_RF<0x82, mnemonic, Xi8, RegMRM>, DisassembleOnly; - def 8mi8 : BinOpMI8_MF, DisassembleOnly; + def 8ri8 : BinOpRI8_RF<0x82, mnemonic, Xi8, RegMRM>, DisassembleOnly; + def 8mi8 : BinOpMI8_MF, DisassembleOnly; } - def 8i8 : BinOpAI_AF; - def 16i16 : BinOpAI_AF, OpSize16; - def 32i32 : BinOpAI_AF, OpSize32; - def 64i32 : BinOpAI_AF; + def 8i8 : BinOpAI_AF; + def 16i16 : BinOpAI_AF, OpSize16; + def 32i32 : BinOpAI_AF, OpSize32; + def 64i32 : BinOpAI_AF; } /// ArithBinOp_RFF - This is an arithmetic binary operator where the pattern is @@ -995,17 +991,13 @@ multiclass ArithBinOp_RFF BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4, // not in 64-bit mode. let Predicates = [Not64BitMode] in { def 8ri8 : BinOpRI8F_RF<0x82, mnemonic, Xi8, RegMRM>, DisassembleOnly; - def 8mi8 : BinOpMI8F_MF, DisassembleOnly; + def 8mi8 : BinOpMI8F_MF, DisassembleOnly; } - def 8i8 : BinOpAIF_AF; - def 16i16 : BinOpAIF_AF, OpSize16; - def 32i32 : BinOpAIF_AF, OpSize32; - def 64i32 : BinOpAIF_AF; + def 8i8 : BinOpAIF_AF; + def 16i16 : BinOpAIF_AF, OpSize16; + def 32i32 : BinOpAIF_AF, OpSize32; + def 64i32 : BinOpAIF_AF; } /// ArithBinOp_F - This is an arithmetic binary operator where the pattern is @@ -1017,11 +1009,11 @@ multiclass ArithBinOp_F BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4, SDNode opnode, bit CommutableRR, bit ConvertibleToThreeAddress> { let isCommutable = CommutableRR in { - def 8rr : BinOpRR_F; + def 8rr : BinOpRR_F; let isConvertibleToThreeAddress = ConvertibleToThreeAddress in { - def 16rr : BinOpRR_F, OpSize16; - def 32rr : BinOpRR_F, OpSize32; - def 64rr : BinOpRR_F; + def 16rr : BinOpRR_F, OpSize16; + def 32rr : BinOpRR_F, OpSize32; + def 64rr : BinOpRR_F; } // isConvertibleToThreeAddress } // isCommutable @@ -1038,15 +1030,15 @@ multiclass ArithBinOp_F BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4, def 8ri : BinOpRI_F<0x80, mnemonic, Xi8 , opnode, RegMRM>; let isConvertibleToThreeAddress = ConvertibleToThreeAddress in { - // NOTE: These are order specific, we want the ri8 forms to be listed - // first so that they are slightly preferred to the ri forms. - def 16ri8 : BinOpRI8_F<0x83, mnemonic, Xi16, RegMRM>, OpSize16; - def 32ri8 : BinOpRI8_F<0x83, mnemonic, Xi32, RegMRM>, OpSize32; - def 64ri8 : BinOpRI8_F<0x83, mnemonic, Xi64, RegMRM>; - - def 16ri : BinOpRI_F<0x81, mnemonic, Xi16, opnode, RegMRM>, OpSize16; - def 32ri : BinOpRI_F<0x81, mnemonic, Xi32, opnode, RegMRM>, OpSize32; - def 64ri32: BinOpRI_F<0x81, mnemonic, Xi64, opnode, RegMRM>; + // NOTE: These are order specific, we want the ri8 forms to be listed + // first so that they are slightly preferred to the ri forms. + def 16ri8 : BinOpRI8_F<0x83, mnemonic, Xi16, RegMRM>, OpSize16; + def 32ri8 : BinOpRI8_F<0x83, mnemonic, Xi32, RegMRM>, OpSize32; + def 64ri8 : BinOpRI8_F<0x83, mnemonic, Xi64, RegMRM>; + + def 16ri : BinOpRI_F<0x81, mnemonic, Xi16, opnode, RegMRM>, OpSize16; + def 32ri : BinOpRI_F<0x81, mnemonic, Xi32, opnode, RegMRM>, OpSize32; + def 64ri32: BinOpRI_F<0x81, mnemonic, Xi64, opnode, RegMRM>; } def 8mr : BinOpMR_F; @@ -1065,24 +1057,20 @@ multiclass ArithBinOp_F BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4, def 16mi : BinOpMI_F<0x81, mnemonic, Xi16, opnode, MemMRM>, OpSize16; def 32mi : BinOpMI_F<0x81, mnemonic, Xi32, opnode, MemMRM>, OpSize32; let Predicates = [In64BitMode] in - def 64mi32 : BinOpMI_F<0x81, mnemonic, Xi64, opnode, MemMRM>; + def 64mi32 : BinOpMI_F<0x81, mnemonic, Xi64, opnode, MemMRM>; // These are for the disassembler since 0x82 opcode behaves like 0x80, but // not in 64-bit mode. let Predicates = [Not64BitMode] in { - def 8ri8 : BinOpRI8_F<0x82, mnemonic, Xi8, RegMRM>, DisassembleOnly; + def 8ri8 : BinOpRI8_F<0x82, mnemonic, Xi8, RegMRM>, DisassembleOnly; let mayLoad = 1 in - def 8mi8 : BinOpMI8_F; + def 8mi8 : BinOpMI8_F; } - def 8i8 : BinOpAI_F; - def 16i16 : BinOpAI_F, OpSize16; - def 32i32 : BinOpAI_F, OpSize32; - def 64i32 : BinOpAI_F; + def 8i8 : BinOpAI_F; + def 16i16 : BinOpAI_F, OpSize16; + def 32i32 : BinOpAI_F, OpSize32; + def 64i32 : BinOpAI_F; } @@ -1095,18 +1083,18 @@ defm XOR : ArithBinOp_RF<0x31, 0x33, 0x35, "xor", MRM6r, MRM6m, defm ADD : ArithBinOp_RF<0x01, 0x03, 0x05, "add", MRM0r, MRM0m, X86add_flag, add, 1, 1, 1>; let isCompare = 1 in { -defm SUB : ArithBinOp_RF<0x29, 0x2B, 0x2D, "sub", MRM5r, MRM5m, - X86sub_flag, sub, 0, 1, 0>; + defm SUB : ArithBinOp_RF<0x29, 0x2B, 0x2D, "sub", MRM5r, MRM5m, + X86sub_flag, sub, 0, 1, 0>; } // Version of XOR8rr_NOREX that use GR8_NOREX. This is used by the handling of // __builtin_parity where the last step xors an h-register with an l-register. let isCodeGenOnly = 1, hasSideEffects = 0, Constraints = "$src1 = $dst", Defs = [EFLAGS], isCommutable = 1 in -def XOR8rr_NOREX : I<0x30, MRMDestReg, (outs GR8_NOREX:$dst), - (ins GR8_NOREX:$src1, GR8_NOREX:$src2), - "xor{b}\t{$src2, $dst|$dst, $src2}", []>, - Sched<[WriteALU]>; + def XOR8rr_NOREX : I<0x30, MRMDestReg, (outs GR8_NOREX:$dst), + (ins GR8_NOREX:$src1, GR8_NOREX:$src2), + "xor{b}\t{$src2, $dst|$dst, $src2}", []>, + Sched<[WriteALU]>; // Arithmetic. defm ADC : ArithBinOp_RFF<0x11, 0x13, 0x15, "adc", MRM2r, MRM2m, X86adc_flag, @@ -1115,7 +1103,7 @@ defm SBB : ArithBinOp_RFF<0x19, 0x1B, 0x1D, "sbb", MRM3r, MRM3m, X86sbb_flag, 0, 0>; let isCompare = 1 in { -defm CMP : ArithBinOp_F<0x39, 0x3B, 0x3D, "cmp", MRM7r, MRM7m, X86cmp, 0, 0>; + defm CMP : ArithBinOp_F<0x39, 0x3B, 0x3D, "cmp", MRM7r, MRM7m, X86cmp, 0, 0>; } // Patterns to recognize loads on the LHS of an ADC. We can't make X86adc_flag @@ -1299,33 +1287,33 @@ let isCompare = 1 in { // Avoid selecting these and instead use a test+and. Post processing will // combine them. This gives bunch of other patterns that start with // and a chance to match. - def TEST8rr : BinOpRR_F<0x84, "test", Xi8 , null_frag>; - def TEST16rr : BinOpRR_F<0x85, "test", Xi16, null_frag>, OpSize16; - def TEST32rr : BinOpRR_F<0x85, "test", Xi32, null_frag>, OpSize32; - def TEST64rr : BinOpRR_F<0x85, "test", Xi64, null_frag>; + def TEST8rr : BinOpRR_F<0x84, "test", Xi8 , null_frag>; + def TEST16rr : BinOpRR_F<0x85, "test", Xi16, null_frag>, OpSize16; + def TEST32rr : BinOpRR_F<0x85, "test", Xi32, null_frag>, OpSize32; + def TEST64rr : BinOpRR_F<0x85, "test", Xi64, null_frag>; } // isCommutable -def TEST8mr : BinOpMR_F<0x84, "test", Xi8 , null_frag>; -def TEST16mr : BinOpMR_F<0x85, "test", Xi16, null_frag>, OpSize16; -def TEST32mr : BinOpMR_F<0x85, "test", Xi32, null_frag>, OpSize32; -def TEST64mr : BinOpMR_F<0x85, "test", Xi64, null_frag>; + def TEST8mr : BinOpMR_F<0x84, "test", Xi8 , null_frag>; + def TEST16mr : BinOpMR_F<0x85, "test", Xi16, null_frag>, OpSize16; + def TEST32mr : BinOpMR_F<0x85, "test", Xi32, null_frag>, OpSize32; + def TEST64mr : BinOpMR_F<0x85, "test", Xi64, null_frag>; -def TEST8ri : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>; -def TEST16ri : BinOpRI_F<0xF7, "test", Xi16, X86testpat, MRM0r>, OpSize16; -def TEST32ri : BinOpRI_F<0xF7, "test", Xi32, X86testpat, MRM0r>, OpSize32; -def TEST64ri32 : BinOpRI_F<0xF7, "test", Xi64, X86testpat, MRM0r>; + def TEST8ri : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>; + def TEST16ri : BinOpRI_F<0xF7, "test", Xi16, X86testpat, MRM0r>, OpSize16; + def TEST32ri : BinOpRI_F<0xF7, "test", Xi32, X86testpat, MRM0r>, OpSize32; + def TEST64ri32 : BinOpRI_F<0xF7, "test", Xi64, X86testpat, MRM0r>; -def TEST8mi : BinOpMI_F<0xF6, "test", Xi8 , X86testpat, MRM0m>; -def TEST16mi : BinOpMI_F<0xF7, "test", Xi16, X86testpat, MRM0m>, OpSize16; -def TEST32mi : BinOpMI_F<0xF7, "test", Xi32, X86testpat, MRM0m>, OpSize32; + def TEST8mi : BinOpMI_F<0xF6, "test", Xi8 , X86testpat, MRM0m>; + def TEST16mi : BinOpMI_F<0xF7, "test", Xi16, X86testpat, MRM0m>, OpSize16; + def TEST32mi : BinOpMI_F<0xF7, "test", Xi32, X86testpat, MRM0m>, OpSize32; let Predicates = [In64BitMode] in - def TEST64mi32 : BinOpMI_F<0xF7, "test", Xi64, X86testpat, MRM0m>; + def TEST64mi32 : BinOpMI_F<0xF7, "test", Xi64, X86testpat, MRM0m>; -def TEST8i8 : BinOpAI_F<0xA8, "test", Xi8 , AL, "{$src, %al|al, $src}">; -def TEST16i16 : BinOpAI_F<0xA9, "test", Xi16, AX, "{$src, %ax|ax, $src}">, OpSize16; -def TEST32i32 : BinOpAI_F<0xA9, "test", Xi32, EAX, "{$src, %eax|eax, $src}">, OpSize32; -def TEST64i32 : BinOpAI_F<0xA9, "test", Xi64, RAX, "{$src, %rax|rax, $src}">; + def TEST8i8 : BinOpAI_F<0xA8, "test", Xi8 , AL, "{$src, %al|al, $src}">; + def TEST16i16 : BinOpAI_F<0xA9, "test", Xi16, AX, "{$src, %ax|ax, $src}">, OpSize16; + def TEST32i32 : BinOpAI_F<0xA9, "test", Xi32, EAX, "{$src, %eax|eax, $src}">, OpSize32; + def TEST64i32 : BinOpAI_F<0xA9, "test", Xi64, RAX, "{$src, %rax|rax, $src}">; } // isCompare // Patterns to match a relocImm into the immediate field. @@ -1409,20 +1397,20 @@ multiclass MulX { (ins t.RegClass:$src), "mulx", mulx_args, []>, T8, XD, VEX, VVVV, Sched<[WriteIMulH, sched]>; let mayLoad = 1 in - def rm : ITy<0xF6, MRMSrcMem, t, (outs t.RegClass:$dst1, t.RegClass:$dst2), - (ins t.MemOperand:$src), "mulx", mulx_args, []>, T8, XD, VEX, - VVVV, Sched; + def rm : ITy<0xF6, MRMSrcMem, t, (outs t.RegClass:$dst1, t.RegClass:$dst2), + (ins t.MemOperand:$src), "mulx", mulx_args, []>, T8, XD, VEX, + VVVV, Sched; let Predicates = [In64BitMode] in { - def rr_EVEX : ITy<0xF6, MRMSrcReg, t, - (outs t.RegClass:$dst1, t.RegClass:$dst2), - (ins t.RegClass:$src), "mulx", mulx_args, []>, T8, XD, - EVEX, VVVV, Sched<[WriteIMulH, sched]>; - let mayLoad = 1 in - def rm_EVEX : ITy<0xF6, MRMSrcMem, t, + def rr_EVEX : ITy<0xF6, MRMSrcReg, t, (outs t.RegClass:$dst1, t.RegClass:$dst2), - (ins t.MemOperand:$src), "mulx", mulx_args, []>, T8, XD, - EVEX, VVVV, Sched; + (ins t.RegClass:$src), "mulx", mulx_args, []>, T8, XD, + EVEX, VVVV, Sched<[WriteIMulH, sched]>; + let mayLoad = 1 in + def rm_EVEX : ITy<0xF6, MRMSrcMem, t, + (outs t.RegClass:$dst1, t.RegClass:$dst2), + (ins t.MemOperand:$src), "mulx", mulx_args, []>, T8, XD, + EVEX, VVVV, Sched; } // Pseudo instructions to be used when the low result isn't used. The // instruction is defined to keep the high if both destinations are the same. @@ -1434,10 +1422,10 @@ multiclass MulX { } let Uses = [EDX] in -defm MULX32 : MulX; + defm MULX32 : MulX; let Uses = [RDX] in -defm MULX64 : MulX, REX_W; + defm MULX64 : MulX, REX_W; //===----------------------------------------------------------------------===// // ADCX and ADOX Instructions -- cgit v1.1