From 2b5b57c5cf78af66b5b9f514c4b51b4adc9a80df Mon Sep 17 00:00:00 2001 From: Christudasan Devadasan Date: Tue, 12 Nov 2024 23:30:57 +0530 Subject: [AMDGPU] Skip non-wwm reg implicit-def from bb prolog (#115834) Currently all implicit-def instructions are part of bb prolog. We should only include the wwm-register's implicit definitions into the BB prolog. The other vector class registers' implicit defs when exist at the bb top might cause interference when pushed the LR_split copy insertion downwards. The SplitKit is very strict on altering the insertion points and will assert such instances. --- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 7 +++++-- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 4 ++++ 2 files changed, 9 insertions(+), 2 deletions(-) (limited to 'llvm/lib/Target') diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index ad45af0..c864f03 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -8909,16 +8909,19 @@ bool SIInstrInfo::isBasicBlockPrologue(const MachineInstr &MI, // needed by the prolog. However, the insertions for scalar registers can // always be placed at the BB top as they are independent of the exec mask // value. + const MachineFunction *MF = MI.getParent()->getParent(); bool IsNullOrVectorRegister = true; if (Reg) { - const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); + const MachineRegisterInfo &MRI = MF->getRegInfo(); IsNullOrVectorRegister = !RI.isSGPRClass(RI.getRegClassForReg(MRI, Reg)); } uint16_t Opcode = MI.getOpcode(); + const SIMachineFunctionInfo *MFI = MF->getInfo(); return IsNullOrVectorRegister && (isSGPRSpill(Opcode) || isWWMRegSpillOpcode(Opcode) || - Opcode == AMDGPU::IMPLICIT_DEF || + (Opcode == AMDGPU::IMPLICIT_DEF && + MFI->isWWMReg(MI.getOperand(0).getReg())) || (!MI.isTerminator() && Opcode != AMDGPU::COPY && MI.modifiesRegister(AMDGPU::EXEC, &RI))); } diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h index 018322e..2a75468 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h @@ -596,6 +596,10 @@ public: SMDiagnostic &Error, SMRange &SourceRange); void reserveWWMRegister(Register Reg) { WWMReservedRegs.insert(Reg); } + bool isWWMReg(Register Reg) const { + return Reg.isVirtual() ? checkFlag(Reg, AMDGPU::VirtRegFlag::WWM_REG) + : WWMReservedRegs.contains(Reg); + } void updateNonWWMRegMask(BitVector &RegMask) { NonWWMRegMask = RegMask; } BitVector getNonWWMRegMask() const { return NonWWMRegMask; } -- cgit v1.1