From 2cb48d620ff3e56f4a4179186055a802c34a4bfd Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Sat, 25 Apr 2020 15:58:40 -0700 Subject: [TableGen] Drop deprecated leading # operation (NOP) and replace ## with # --- llvm/lib/Target/SystemZ/SystemZOperands.td | 60 +++++++++++++++--------------- 1 file changed, 30 insertions(+), 30 deletions(-) (limited to 'llvm/lib/Target/SystemZ/SystemZOperands.td') diff --git a/llvm/lib/Target/SystemZ/SystemZOperands.td b/llvm/lib/Target/SystemZ/SystemZOperands.td index bd40f6d..a883daa 100644 --- a/llvm/lib/Target/SystemZ/SystemZOperands.td +++ b/llvm/lib/Target/SystemZ/SystemZOperands.td @@ -22,8 +22,8 @@ class ImmediateTLSAsmOperand } class ImmediateOp : Operand { - let PrintMethod = "print"##asmop##"Operand"; - let DecoderMethod = "decode"##asmop##"Operand"; + let PrintMethod = "print"#asmop#"Operand"; + let DecoderMethod = "decode"#asmop#"Operand"; let ParserMatchClass = !cast(asmop); let OperandType = "OPERAND_IMMEDIATE"; } @@ -52,14 +52,14 @@ multiclass Immediate { // Constructs an asm operand for a PC-relative address. SIZE says how // many bits there are. -class PCRelAsmOperand : ImmediateAsmOperand<"PCRel"##size> { +class PCRelAsmOperand : ImmediateAsmOperand<"PCRel"#size> { let PredicateMethod = "isImm"; - let ParserMethod = "parsePCRel"##size; + let ParserMethod = "parsePCRel"#size; } class PCRelTLSAsmOperand - : ImmediateTLSAsmOperand<"PCRelTLS"##size> { + : ImmediateTLSAsmOperand<"PCRelTLS"#size> { let PredicateMethod = "isImmTLS"; - let ParserMethod = "parsePCRelTLS"##size; + let ParserMethod = "parsePCRelTLS"#size; } // Constructs an operand for a PC-relative address with address type VT. @@ -92,9 +92,9 @@ class PCRelAddress class AddressAsmOperand : AsmOperandClass { - let Name = format##bitsize##"Disp"##dispsize##length; - let ParserMethod = "parse"##format##bitsize; - let RenderMethod = "add"##format##"Operands"; + let Name = format#bitsize#"Disp"#dispsize#length; + let ParserMethod = "parse"#format#bitsize; + let RenderMethod = "add"#format#"Operands"; } // Constructs an instruction operand for an addressing mode. FORMAT, @@ -103,15 +103,15 @@ class AddressAsmOperand - : Operand("i"##bitsize)> { - let PrintMethod = "print"##format##"Operand"; - let EncoderMethod = "get"##format##dispsize##length##"Encoding"; + : Operand("i"#bitsize)> { + let PrintMethod = "print"#format#"Operand"; + let EncoderMethod = "get"#format#dispsize#length#"Encoding"; let DecoderMethod = - "decode"##format##bitsize##"Disp"##dispsize##length##"Operand"; + "decode"#format#bitsize#"Disp"#dispsize#length#"Operand"; let OperandType = "OPERAND_MEMORY"; let MIOperandInfo = operands; let ParserMatchClass = - !cast(format##bitsize##"Disp"##dispsize##length); + !cast(format#bitsize#"Disp"#dispsize#length); } // Constructs both a DAG pattern and instruction operand for an addressing mode. @@ -126,45 +126,45 @@ class AddressOperand - : ComplexPattern("i"##bitsize), numops, - "select"##seltype##dispsize##suffix##length, + : ComplexPattern("i"#bitsize), numops, + "select"#seltype#dispsize#suffix#length, [add, sub, or, frameindex, z_adjdynalloc]>, AddressOperand; // An addressing mode with a base and displacement but no index. class BDMode : AddressingMode("ADDR"##bitsize), - !cast("disp"##dispsize##"imm"##bitsize))>; + (ops !cast("ADDR"#bitsize), + !cast("disp"#dispsize#"imm"#bitsize))>; // An addressing mode with a base, displacement and index. class BDXMode : AddressingMode("ADDR"##bitsize), - !cast("disp"##dispsize##"imm"##bitsize), - !cast("ADDR"##bitsize))>; + (ops !cast("ADDR"#bitsize), + !cast("disp"#dispsize#"imm"#bitsize), + !cast("ADDR"#bitsize))>; // A BDMode paired with an immediate length operand of LENSIZE bits. class BDLMode - : AddressingMode("ADDR"##bitsize), - !cast("disp"##dispsize##"imm"##bitsize), - !cast("imm"##bitsize))>; + (ops !cast("ADDR"#bitsize), + !cast("disp"#dispsize#"imm"#bitsize), + !cast("imm"#bitsize))>; // A BDMode paired with a register length operand. class BDRMode : AddressingMode("ADDR"##bitsize), - !cast("disp"##dispsize##"imm"##bitsize), - !cast("GR"##bitsize))>; + (ops !cast("ADDR"#bitsize), + !cast("disp"#dispsize#"imm"#bitsize), + !cast("GR"#bitsize))>; // An addressing mode with a base, displacement and a vector index. class BDVMode : AddressOperand("ADDR"##bitsize), - !cast("disp"##dispsize##"imm"##bitsize), + (ops !cast("ADDR"#bitsize), + !cast("disp"#dispsize#"imm"#bitsize), !cast("VR128"))>; //===----------------------------------------------------------------------===// -- cgit v1.1