From 71bfec762bd970e7834f58c158ddc15f93402d7a Mon Sep 17 00:00:00 2001 From: Michael Maitland Date: Thu, 24 Aug 2023 15:37:27 -0700 Subject: Revert "[TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics" This reverts commit 5b854f2c23ea1b000cb4cac4c0fea77326c03d43. Build still failing. --- llvm/lib/MCA/HardwareUnits/ResourceManager.cpp | 6 +++--- llvm/lib/MCA/HardwareUnits/Scheduler.cpp | 4 ++-- llvm/lib/MCA/InstrBuilder.cpp | 8 ++++---- llvm/lib/MCA/Stages/ExecuteStage.cpp | 2 +- llvm/lib/MCA/Stages/InstructionTables.cpp | 5 ++--- llvm/lib/MCA/Support.cpp | 10 +++++----- 6 files changed, 17 insertions(+), 18 deletions(-) (limited to 'llvm/lib/MCA') diff --git a/llvm/lib/MCA/HardwareUnits/ResourceManager.cpp b/llvm/lib/MCA/HardwareUnits/ResourceManager.cpp index 8d99695..393548d 100644 --- a/llvm/lib/MCA/HardwareUnits/ResourceManager.cpp +++ b/llvm/lib/MCA/HardwareUnits/ResourceManager.cpp @@ -346,7 +346,7 @@ uint64_t ResourceManager::checkAvailability(const InstrDesc &Desc) const { void ResourceManager::issueInstruction( const InstrDesc &Desc, - SmallVectorImpl> &Pipes) { + SmallVectorImpl> &Pipes) { for (const std::pair &R : Desc.Resources) { const CycleSegment &CS = R.second.CS; if (!CS.size()) { @@ -359,8 +359,8 @@ void ResourceManager::issueInstruction( ResourceRef Pipe = selectPipe(R.first); use(Pipe); BusyResources[Pipe] += CS.size(); - Pipes.emplace_back(std::pair( - Pipe, ReleaseAtCycles(CS.size()))); + Pipes.emplace_back(std::pair( + Pipe, ResourceCycles(CS.size()))); } else { assert((llvm::popcount(R.first) > 1) && "Expected a group!"); // Mark this group as reserved. diff --git a/llvm/lib/MCA/HardwareUnits/Scheduler.cpp b/llvm/lib/MCA/HardwareUnits/Scheduler.cpp index a9bbf69..31ea751 100644 --- a/llvm/lib/MCA/HardwareUnits/Scheduler.cpp +++ b/llvm/lib/MCA/HardwareUnits/Scheduler.cpp @@ -69,7 +69,7 @@ Scheduler::Status Scheduler::isAvailable(const InstRef &IR) { void Scheduler::issueInstructionImpl( InstRef &IR, - SmallVectorImpl> &UsedResources) { + SmallVectorImpl> &UsedResources) { Instruction *IS = IR.getInstruction(); const InstrDesc &D = IS->getDesc(); @@ -98,7 +98,7 @@ void Scheduler::issueInstructionImpl( // Release the buffered resources and issue the instruction. void Scheduler::issueInstruction( InstRef &IR, - SmallVectorImpl> &UsedResources, + SmallVectorImpl> &UsedResources, SmallVectorImpl &PendingInstructions, SmallVectorImpl &ReadyInstructions) { const Instruction &Inst = *IR.getInstruction(); diff --git a/llvm/lib/MCA/InstrBuilder.cpp b/llvm/lib/MCA/InstrBuilder.cpp index 1a82e45..bddd370 100644 --- a/llvm/lib/MCA/InstrBuilder.cpp +++ b/llvm/lib/MCA/InstrBuilder.cpp @@ -69,7 +69,7 @@ static void initializeUsedResources(InstrDesc &ID, for (unsigned I = 0, E = SCDesc.NumWriteProcResEntries; I < E; ++I) { const MCWriteProcResEntry *PRE = STI.getWriteProcResBegin(&SCDesc) + I; const MCProcResourceDesc &PR = *SM.getProcResource(PRE->ProcResourceIdx); - if (!PRE->ReleaseAtCycle) { + if (!PRE->Cycles) { #ifndef NDEBUG WithColor::warning() << "Ignoring invalid write of zero cycles on processor resource " @@ -89,11 +89,11 @@ static void initializeUsedResources(InstrDesc &ID, AllInOrderResources &= (PR.BufferSize <= 1); } - CycleSegment RCy(0, PRE->ReleaseAtCycle, false); + CycleSegment RCy(0, PRE->Cycles, false); Worklist.emplace_back(ResourcePlusCycles(Mask, ResourceUsage(RCy))); if (PR.SuperIdx) { uint64_t Super = ProcResourceMasks[PR.SuperIdx]; - SuperResources[Super] += PRE->ReleaseAtCycle; + SuperResources[Super] += PRE->Cycles; } } @@ -156,7 +156,7 @@ static void initializeUsedResources(InstrDesc &ID, // is reserved. For example (on target x86; cpu Haswell): // // SchedWriteRes<[HWPort0, HWPort1, HWPort01]> { - // let ReleaseAtCycles = [2, 2, 3]; + // let ResourceCycles = [2, 2, 3]; // } // // This means: diff --git a/llvm/lib/MCA/Stages/ExecuteStage.cpp b/llvm/lib/MCA/Stages/ExecuteStage.cpp index 7714d4f..6d36c4a 100644 --- a/llvm/lib/MCA/Stages/ExecuteStage.cpp +++ b/llvm/lib/MCA/Stages/ExecuteStage.cpp @@ -196,7 +196,7 @@ Error ExecuteStage::execute(InstRef &IR) { // Reserve a slot in each buffered resource. Also, mark units with // BufferSize=0 as reserved. Resources with a buffer size of zero will only - // be released after MCIS is issued, and all the ReleaseAtCycles for those + // be released after MCIS is issued, and all the ResourceCycles for those // units have been consumed. bool IsReadyInstruction = HWS.dispatch(IR); const Instruction &Inst = *IR.getInstruction(); diff --git a/llvm/lib/MCA/Stages/InstructionTables.cpp b/llvm/lib/MCA/Stages/InstructionTables.cpp index 937cc7d..a842b52 100644 --- a/llvm/lib/MCA/Stages/InstructionTables.cpp +++ b/llvm/lib/MCA/Stages/InstructionTables.cpp @@ -38,7 +38,7 @@ Error InstructionTables::execute(InstRef &IR) { for (unsigned I = 0, E = NumUnits; I < E; ++I) { ResourceRef ResourceUnit = std::make_pair(Index, 1U << I); UsedResources.emplace_back( - std::make_pair(ResourceUnit, ReleaseAtCycles(Cycles, NumUnits))); + std::make_pair(ResourceUnit, ResourceCycles(Cycles, NumUnits))); } continue; } @@ -53,8 +53,7 @@ Error InstructionTables::execute(InstRef &IR) { for (unsigned I2 = 0, E2 = SubUnit.NumUnits; I2 < E2; ++I2) { ResourceRef ResourceUnit = std::make_pair(SubUnitIdx, 1U << I2); UsedResources.emplace_back(std::make_pair( - ResourceUnit, - ReleaseAtCycles(Cycles, NumUnits * SubUnit.NumUnits))); + ResourceUnit, ResourceCycles(Cycles, NumUnits * SubUnit.NumUnits))); } } } diff --git a/llvm/lib/MCA/Support.cpp b/llvm/lib/MCA/Support.cpp index f8b8a2d..517738c 100644 --- a/llvm/lib/MCA/Support.cpp +++ b/llvm/lib/MCA/Support.cpp @@ -21,7 +21,7 @@ namespace mca { #define DEBUG_TYPE "llvm-mca" -ReleaseAtCycles &ReleaseAtCycles::operator+=(const ReleaseAtCycles &RHS) { +ResourceCycles &ResourceCycles::operator+=(const ResourceCycles &RHS) { if (Denominator == RHS.Denominator) Numerator += RHS.Numerator; else { @@ -92,18 +92,18 @@ double computeBlockRThroughput(const MCSchedModel &SM, unsigned DispatchWidth, // The number of available resource units affects the resource pressure // distribution, as well as how many blocks can be executed every cycle. for (unsigned I = 0, E = SM.getNumProcResourceKinds(); I < E; ++I) { - unsigned ReleaseAtCycles = ProcResourceUsage[I]; - if (!ReleaseAtCycles) + unsigned ResourceCycles = ProcResourceUsage[I]; + if (!ResourceCycles) continue; const MCProcResourceDesc &MCDesc = *SM.getProcResource(I); - double Throughput = static_cast(ReleaseAtCycles) / MCDesc.NumUnits; + double Throughput = static_cast(ResourceCycles) / MCDesc.NumUnits; Max = std::max(Max, Throughput); } // The block reciprocal throughput is computed as the MAX of: // - (NumMicroOps / DispatchWidth) - // - (NumUnits / ReleaseAtCycles) for every consumed processor resource. + // - (NumUnits / ResourceCycles) for every consumed processor resource. return Max; } -- cgit v1.1