From c22db56d7766fe704298b81b548fa6004a9d312c Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 7 Mar 2025 07:44:08 +0700 Subject: PeepholeOpt: Remove subreg def check for bitcast (#130086) Subregister defs are illegal in SSA. Surprisingly this enables folding into subregister insert patterns in one test. --- llvm/lib/CodeGen/PeepholeOptimizer.cpp | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) (limited to 'llvm/lib/CodeGen/PeepholeOptimizer.cpp') diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp b/llvm/lib/CodeGen/PeepholeOptimizer.cpp index 4d0fd86..ec8e97f 100644 --- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp +++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp @@ -1923,11 +1923,8 @@ ValueTrackerResult ValueTracker::getNextSourceFromBitcast() { // Bitcasts with more than one def are not supported. if (Def->getDesc().getNumDefs() != 1) return ValueTrackerResult(); - const MachineOperand DefOp = Def->getOperand(DefIdx); - if (DefOp.getSubReg() != DefSubReg) - // If we look for a different subreg, it means we want a subreg of the src. - // Bails as we do not support composing subregs yet. - return ValueTrackerResult(); + + assert(!Def->getOperand(DefIdx).getSubReg() && "no subregister defs in SSA"); unsigned SrcIdx = Def->getNumOperands(); for (unsigned OpIdx = DefIdx + 1, EndOpIdx = SrcIdx; OpIdx != EndOpIdx; @@ -1950,6 +1947,8 @@ ValueTrackerResult ValueTracker::getNextSourceFromBitcast() { if (SrcIdx >= Def->getNumOperands()) return ValueTrackerResult(); + const MachineOperand &DefOp = Def->getOperand(DefIdx); + // Stop when any user of the bitcast is a SUBREG_TO_REG, replacing with a COPY // will break the assumed guarantees for the upper bits. for (const MachineInstr &UseMI : MRI.use_nodbg_instructions(DefOp.getReg())) { -- cgit v1.1