From 05a7b22a0132bebe99aabee591d3acc99d793ae1 Mon Sep 17 00:00:00 2001 From: Jianjian Guan Date: Wed, 27 Mar 2024 14:16:03 +0800 Subject: [RISCV] Add areInlineCompatible for riscv target (#86639) Inline a callee if its target-features are a subset of the callers target-features. --- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 14 +++++++++ llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h | 3 ++ .../Inline/RISCV/inline-target-features.ll | 34 ++++++++++++++++++++++ llvm/test/Transforms/Inline/RISCV/lit.local.cfg | 2 ++ 4 files changed, 53 insertions(+) create mode 100644 llvm/test/Transforms/Inline/RISCV/inline-target-features.ll create mode 100644 llvm/test/Transforms/Inline/RISCV/lit.local.cfg diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp index df289be..000d01b 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp @@ -1676,3 +1676,17 @@ bool RISCVTTIImpl::isLegalMaskedCompressStore(Type *DataTy, Align Alignment) { return false; return true; } + +bool RISCVTTIImpl::areInlineCompatible(const Function *Caller, + const Function *Callee) const { + const TargetMachine &TM = getTLI()->getTargetMachine(); + + const FeatureBitset &CallerBits = + TM.getSubtargetImpl(*Caller)->getFeatureBits(); + const FeatureBitset &CalleeBits = + TM.getSubtargetImpl(*Callee)->getFeatureBits(); + + // Inline a callee if its target-features are a subset of the callers + // target-features. + return (CallerBits & CalleeBits) == CalleeBits; +} diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h index 8daf684..ac32aea 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h @@ -60,6 +60,9 @@ public: : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)), TLI(ST->getTargetLowering()) {} + bool areInlineCompatible(const Function *Caller, + const Function *Callee) const; + /// Return the cost of materializing an immediate for a value operand of /// a store instruction. InstructionCost getStoreImmCost(Type *VecTy, TTI::OperandValueInfo OpInfo, diff --git a/llvm/test/Transforms/Inline/RISCV/inline-target-features.ll b/llvm/test/Transforms/Inline/RISCV/inline-target-features.ll new file mode 100644 index 0000000..b626a22 --- /dev/null +++ b/llvm/test/Transforms/Inline/RISCV/inline-target-features.ll @@ -0,0 +1,34 @@ +; RUN: opt < %s -mtriple=riscv64-unknown-linux-gnu -S -passes=inline | FileCheck %s +; RUN: opt < %s -mtriple=riscv64-unknown-linux-gnu -S -passes='cgscc(inline)' | FileCheck %s +; Check that we only inline when we have compatible target attributes. + +target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128" +target triple = "riscv64-unknown-linux-gnu" + +define i32 @foo() #0 { +entry: + %call = call i32 (...) @baz() + ret i32 %call +; CHECK-LABEL: foo +; CHECK: call i32 (...) @baz() +} +declare i32 @baz(...) #0 + +define i32 @bar() #1 { +entry: + %call = call i32 @foo() + ret i32 %call +; CHECK-LABEL: bar +; CHECK: call i32 (...) @baz() +} + +define i32 @qux() #0 { +entry: + %call = call i32 @bar() + ret i32 %call +; CHECK-LABEL: qux +; CHECK: call i32 @bar() +} + +attributes #0 = { "target-cpu"="generic-rv64" "target-features"="+f,+d" } +attributes #1 = { "target-cpu"="generic-rv64" "target-features"="+f,+d,+m,+v" } diff --git a/llvm/test/Transforms/Inline/RISCV/lit.local.cfg b/llvm/test/Transforms/Inline/RISCV/lit.local.cfg new file mode 100644 index 0000000..1735174 --- /dev/null +++ b/llvm/test/Transforms/Inline/RISCV/lit.local.cfg @@ -0,0 +1,2 @@ +if not "RISCV" in config.root.targets: + config.unsupported = True -- cgit v1.1 From 577e0ef94fb0b4ba9f97a6f58a1961f7ba247d21 Mon Sep 17 00:00:00 2001 From: Alina Sbirlea Date: Tue, 26 Mar 2024 23:24:02 -0700 Subject: [clang][AST] Silence unused-value warnings in unittest DeclPrinterTest --- clang/unittests/AST/DeclPrinterTest.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/clang/unittests/AST/DeclPrinterTest.cpp b/clang/unittests/AST/DeclPrinterTest.cpp index 07fa02b..8a29d05 100644 --- a/clang/unittests/AST/DeclPrinterTest.cpp +++ b/clang/unittests/AST/DeclPrinterTest.cpp @@ -1391,7 +1391,7 @@ TEST(DeclPrinter, TestCXXRecordDecl17) { "struct X {};" "Z A;", "A", "Z A")); - [](PrintingPolicy &Policy) { Policy.SuppressTagKeyword = false; }; + (void)[](PrintingPolicy &Policy) { Policy.SuppressTagKeyword = false; }; } TEST(DeclPrinter, TestCXXRecordDecl18) { @@ -1402,7 +1402,7 @@ TEST(DeclPrinter, TestCXXRecordDecl18) { "struct Y{};" "Y, 2> B;", "B", "Y, 2> B")); - [](PrintingPolicy &Policy) { Policy.SuppressTagKeyword = false; }; + (void)[](PrintingPolicy &Policy) { Policy.SuppressTagKeyword = false; }; } TEST(DeclPrinter, TestCXXRecordDecl19) { @@ -1413,7 +1413,7 @@ TEST(DeclPrinter, TestCXXRecordDecl19) { "struct Y{};" "Y, 2> B;", "B", "Y, 2> B")); - [](PrintingPolicy &Policy) { Policy.SuppressTagKeyword = true; }; + (void)[](PrintingPolicy &Policy) { Policy.SuppressTagKeyword = true; }; } TEST(DeclPrinter, TestCXXRecordDecl20) { ASSERT_TRUE(PrintedDeclCXX98Matches( @@ -1432,7 +1432,7 @@ TEST(DeclPrinter, TestCXXRecordDecl20) { "Outer, 5>::NestedStruct nestedInstance(100);", "nestedInstance", "Outer, 5>::NestedStruct nestedInstance(100)")); - [](PrintingPolicy &Policy) { Policy.SuppressTagKeyword = false; }; + (void)[](PrintingPolicy &Policy) { Policy.SuppressTagKeyword = false; }; } TEST(DeclPrinter, TestCXXRecordDecl21) { @@ -1452,7 +1452,7 @@ TEST(DeclPrinter, TestCXXRecordDecl21) { "Outer, 5>::NestedStruct nestedInstance(100);", "nestedInstance", "Outer, 5>::NestedStruct nestedInstance(100)")); - [](PrintingPolicy &Policy) { Policy.SuppressTagKeyword = true; }; + (void)[](PrintingPolicy &Policy) { Policy.SuppressTagKeyword = true; }; } TEST(DeclPrinter, TestFunctionParamUglified) { -- cgit v1.1