From b8ead2198f27924f91b90b6c104c1234ccc8972e Mon Sep 17 00:00:00 2001 From: Gulfem Savrun Yeniceri Date: Mon, 1 Apr 2024 18:25:02 +0000 Subject: Revert "[CodeGen] Fix register pressure computation in MachinePipeliner (#87030)" This reverts commit a4dec9d6bc67c4d8fbd4a4f54ffaa0399def9627 because the test failed in the following builder: https://luci-milo.appspot.com/ui/p/fuchsia/builders/prod/clang-linux-x64/b8751864477467126481/overview --- llvm/lib/CodeGen/MachinePipeliner.cpp | 2 +- llvm/test/CodeGen/AArch64/sms-regpress.mir | 158 ------------------------ llvm/test/CodeGen/PowerPC/sms-regpress.mir | 186 +++++++++++++++++++++++++---- 3 files changed, 166 insertions(+), 180 deletions(-) delete mode 100644 llvm/test/CodeGen/AArch64/sms-regpress.mir diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp index b9c6765..eb42a78 100644 --- a/llvm/lib/CodeGen/MachinePipeliner.cpp +++ b/llvm/lib/CodeGen/MachinePipeliner.cpp @@ -1268,7 +1268,7 @@ private: // Calculate the upper limit of each pressure set void computePressureSetLimit(const RegisterClassInfo &RCI) { for (unsigned PSet = 0; PSet < PSetNum; PSet++) - PressureSetLimit[PSet] = TRI->getRegPressureSetLimit(MF, PSet); + PressureSetLimit[PSet] = RCI.getRegPressureSetLimit(PSet); // We assume fixed registers, such as stack pointer, are already in use. // Therefore subtracting the weight of the fixed registers from the limit of diff --git a/llvm/test/CodeGen/AArch64/sms-regpress.mir b/llvm/test/CodeGen/AArch64/sms-regpress.mir deleted file mode 100644 index ad98d5c..0000000 --- a/llvm/test/CodeGen/AArch64/sms-regpress.mir +++ /dev/null @@ -1,158 +0,0 @@ -# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -aarch64-enable-pipeliner -pipeliner-max-mii=40 -pipeliner-register-pressure -pipeliner-ii-search-range=30 -debug-only=pipeliner 2>&1 | FileCheck %s - -# Check that if the register pressure is too high, the schedule is rejected, II is incremented, and scheduling continues. -# The specific value of II is not important. - -# CHECK: {{^ *}}Try to schedule with {{[0-9]+$}} -# CHECK: {{^ *}}Rejected the schedule because of too high register pressure{{$}} -# CHECK: {{^ *}}Try to schedule with {{[0-9]+$}} -# CHECK: {{^ *}}Schedule Found? 1 (II={{[0-9]+}}){{$}} - ---- | - target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" - - define dso_local double @kernel(ptr nocapture noundef readonly %a, ptr nocapture noundef readonly %b, i32 noundef %n) local_unnamed_addr { - entry: - %0 = load double, ptr %a, align 8 - %arrayidx1 = getelementptr inbounds i8, ptr %a, i64 8 - %1 = load double, ptr %arrayidx1, align 8 - %cmp133 = icmp sgt i32 %n, 0 - br i1 %cmp133, label %for.body.preheader, label %for.cond.cleanup - - for.body.preheader: ; preds = %entry - %wide.trip.count = zext nneg i32 %n to i64 - br label %for.body - - for.cond.cleanup: ; preds = %for.body, %entry - %res.0.lcssa = phi double [ 0.000000e+00, %entry ], [ %add54, %for.body ] - ret double %res.0.lcssa - - for.body: ; preds = %for.body.preheader, %for.body - %lsr.iv137 = phi i64 [ %wide.trip.count, %for.body.preheader ], [ %lsr.iv.next, %for.body ] - %lsr.iv = phi ptr [ %b, %for.body.preheader ], [ %scevgep, %for.body ] - %res.0135 = phi double [ 0.000000e+00, %for.body.preheader ], [ %add54, %for.body ] - %2 = load double, ptr %lsr.iv, align 8 - %3 = tail call double @llvm.fmuladd.f64(double %0, double %2, double %0) - %4 = tail call double @llvm.fmuladd.f64(double %3, double %2, double %3) - %5 = tail call double @llvm.fmuladd.f64(double %4, double %2, double %4) - %6 = tail call double @llvm.fmuladd.f64(double %5, double %2, double %5) - %7 = tail call double @llvm.fmuladd.f64(double %6, double %2, double %6) - %8 = tail call double @llvm.fmuladd.f64(double %7, double %2, double %7) - %9 = tail call double @llvm.fmuladd.f64(double %8, double %2, double %8) - %10 = tail call double @llvm.fmuladd.f64(double %9, double %2, double %9) - %11 = tail call double @llvm.fmuladd.f64(double %10, double %2, double %10) - %12 = tail call double @llvm.fmuladd.f64(double %11, double %2, double %11) - %13 = tail call double @llvm.fmuladd.f64(double %12, double %2, double %12) - %14 = tail call double @llvm.fmuladd.f64(double %13, double %2, double %13) - %15 = tail call double @llvm.fmuladd.f64(double %14, double %2, double %14) - %16 = tail call double @llvm.fmuladd.f64(double %15, double %2, double %15) - %17 = tail call double @llvm.fmuladd.f64(double %16, double %2, double %16) - %18 = tail call double @llvm.fmuladd.f64(double %17, double %2, double %17) - %add = fadd double %17, %18 - %19 = tail call double @llvm.fmuladd.f64(double %18, double %2, double %add) - %add35 = fadd double %10, %19 - %20 = tail call double @llvm.fmuladd.f64(double %3, double %2, double %add35) - %add38 = fadd double %11, %20 - %21 = tail call double @llvm.fmuladd.f64(double %4, double %2, double %add38) - %add41 = fadd double %12, %21 - %22 = tail call double @llvm.fmuladd.f64(double %5, double %2, double %add41) - %add44 = fadd double %14, %15 - %add45 = fadd double %13, %add44 - %add46 = fadd double %add45, %22 - %23 = tail call double @llvm.fmuladd.f64(double %6, double %2, double %add46) - %mul = fmul double %2, %7 - %mul51 = fmul double %1, %mul - %24 = tail call double @llvm.fmuladd.f64(double %mul51, double %9, double %23) - %25 = tail call double @llvm.fmuladd.f64(double %8, double %1, double %24) - %add54 = fadd double %res.0135, %25 - %scevgep = getelementptr i8, ptr %lsr.iv, i64 8 - %lsr.iv.next = add nsw i64 %lsr.iv137, -1 - %exitcond.not = icmp eq i64 %lsr.iv.next, 0 - br i1 %exitcond.not, label %for.cond.cleanup, label %for.body - } - - declare double @llvm.fmuladd.f64(double, double, double) - -... ---- -name: kernel -tracksRegLiveness: true -liveins: - - { reg: '$x0', virtual-reg: '%10' } - - { reg: '$x1', virtual-reg: '%11' } - - { reg: '$w2', virtual-reg: '%12' } -body: | - bb.0.entry: - successors: %bb.1, %bb.4 - liveins: $x0, $x1, $w2 - - %12:gpr32common = COPY $w2 - %11:gpr64 = COPY $x1 - %10:gpr64common = COPY $x0 - dead $wzr = SUBSWri %12, 1, 0, implicit-def $nzcv - Bcc 10, %bb.1, implicit $nzcv - - bb.4: - %13:fpr64 = FMOVD0 - B %bb.2 - - bb.1.for.body.preheader: - %0:fpr64 = LDRDui %10, 0 :: (load (s64) from %ir.a) - %1:fpr64 = LDRDui %10, 1 :: (load (s64) from %ir.arrayidx1) - %16:gpr32 = ORRWrs $wzr, %12, 0 - %2:gpr64all = SUBREG_TO_REG 0, killed %16, %subreg.sub_32 - %15:fpr64 = FMOVD0 - B %bb.3 - - bb.2.for.cond.cleanup: - %3:fpr64 = PHI %13, %bb.4, %7, %bb.3 - $d0 = COPY %3 - RET_ReallyLR implicit $d0 - - bb.3.for.body: - successors: %bb.2, %bb.3 - - %4:gpr64sp = PHI %2, %bb.1, %9, %bb.3 - %5:gpr64sp = PHI %11, %bb.1, %8, %bb.3 - %6:fpr64 = PHI %15, %bb.1, %7, %bb.3 - early-clobber %17:gpr64sp, %18:fpr64 = LDRDpost %5, 8 :: (load (s64) from %ir.lsr.iv) - %19:fpr64 = nofpexcept FMADDDrrr %0, %18, %0, implicit $fpcr - %20:fpr64 = nofpexcept FMADDDrrr %19, %18, %19, implicit $fpcr - %21:fpr64 = nofpexcept FMADDDrrr %20, %18, %20, implicit $fpcr - %22:fpr64 = nofpexcept FMADDDrrr %21, %18, %21, implicit $fpcr - %23:fpr64 = nofpexcept FMADDDrrr %22, %18, %22, implicit $fpcr - %24:fpr64 = nofpexcept FMADDDrrr %23, %18, %23, implicit $fpcr - %25:fpr64 = nofpexcept FMADDDrrr %24, %18, %24, implicit $fpcr - %26:fpr64 = nofpexcept FMADDDrrr %25, %18, %25, implicit $fpcr - %27:fpr64 = nofpexcept FMADDDrrr %26, %18, %26, implicit $fpcr - %28:fpr64 = nofpexcept FMADDDrrr %27, %18, %27, implicit $fpcr - %29:fpr64 = nofpexcept FMADDDrrr %28, %18, %28, implicit $fpcr - %30:fpr64 = nofpexcept FMADDDrrr %29, %18, %29, implicit $fpcr - %31:fpr64 = nofpexcept FMADDDrrr %30, %18, %30, implicit $fpcr - %32:fpr64 = nofpexcept FMADDDrrr %31, %18, %31, implicit $fpcr - %33:fpr64 = nofpexcept FMADDDrrr %32, %18, %32, implicit $fpcr - %34:fpr64 = nofpexcept FMADDDrrr %33, %18, %33, implicit $fpcr - %35:fpr64 = nofpexcept FADDDrr %33, %34, implicit $fpcr - %36:fpr64 = nofpexcept FMADDDrrr %34, %18, killed %35, implicit $fpcr - %37:fpr64 = nofpexcept FADDDrr %26, killed %36, implicit $fpcr - %38:fpr64 = nofpexcept FMADDDrrr %19, %18, killed %37, implicit $fpcr - %39:fpr64 = nofpexcept FADDDrr %27, killed %38, implicit $fpcr - %40:fpr64 = nofpexcept FMADDDrrr %20, %18, killed %39, implicit $fpcr - %41:fpr64 = nofpexcept FADDDrr %28, killed %40, implicit $fpcr - %42:fpr64 = nofpexcept FMADDDrrr %21, %18, killed %41, implicit $fpcr - %43:fpr64 = nofpexcept FADDDrr %30, %31, implicit $fpcr - %44:fpr64 = nofpexcept FADDDrr %29, killed %43, implicit $fpcr - %45:fpr64 = nofpexcept FADDDrr killed %44, killed %42, implicit $fpcr - %46:fpr64 = nofpexcept FMADDDrrr %22, %18, killed %45, implicit $fpcr - %47:fpr64 = nofpexcept FMULDrr %18, %23, implicit $fpcr - %48:fpr64 = nofpexcept FMULDrr %1, killed %47, implicit $fpcr - %49:fpr64 = nofpexcept FMADDDrrr killed %48, %25, killed %46, implicit $fpcr - %50:fpr64 = nofpexcept FMADDDrrr %24, %1, killed %49, implicit $fpcr - %7:fpr64 = nofpexcept FADDDrr %6, killed %50, implicit $fpcr - %8:gpr64all = COPY %17 - %51:gpr64 = nsw SUBSXri %4, 1, 0, implicit-def $nzcv - %9:gpr64all = COPY %51 - Bcc 0, %bb.2, implicit $nzcv - B %bb.3 - -... diff --git a/llvm/test/CodeGen/PowerPC/sms-regpress.mir b/llvm/test/CodeGen/PowerPC/sms-regpress.mir index b01115c..cebd78a 100644 --- a/llvm/test/CodeGen/PowerPC/sms-regpress.mir +++ b/llvm/test/CodeGen/PowerPC/sms-regpress.mir @@ -1,30 +1,41 @@ -# RUN: llc --verify-machineinstrs -mcpu=pwr9 -o - %s -run-pass=pipeliner -ppc-enable-pipeliner -pipeliner-register-pressure -pipeliner-max-mii=50 -pipeliner-ii-search-range=30 -pipeliner-max-stages=10 -debug-only=pipeliner 2>&1 | FileCheck %s +# RUN: llc --verify-machineinstrs -mcpu=pwr9 -o - %s -run-pass=pipeliner -ppc-enable-pipeliner -pipeliner-register-pressure -pipeliner-max-mii=50 -pipeliner-ii-search-range=30 -pipeliner-max-stages=10 -debug-only=pipeliner 2>&1 | FileCheck %s # REQUIRES: asserts # Check that if the register pressure is too high, the schedule is rejected, II is incremented, and scheduling continues. # The specific value of II is not important. -# CHECK: {{^ *}}Try to schedule with {{[0-9]+$}} -# CHECK: {{^ *}}Rejected the schedule because of too high register pressure{{$}} -# CHECK: {{^ *}}Try to schedule with {{[0-9]+$}} -# CHECK: {{^ *}}Schedule Found? 1 (II={{[0-9]+}}){{$}} +# CHECK: Try to schedule with 21 +# CHECK: Can't schedule +# CHECK: Try to schedule with 22 +# CHECK: Can't schedule +# CHECK: Try to schedule with 23 +# CHECK: Rejected the schedule because of too high register pressure +# CHECK: Try to schedule with 24 +# CHECK: Rejected the schedule because of too high register pressure +# CHECK: Try to schedule with 25 +# CHECK: Rejected the schedule because of too high register pressure +# CHECK: Try to schedule with 26 +# CHECK: Schedule Found? 1 (II=26) --- | + ; ModuleID = 'a.ll' + source_filename = "a.c" target datalayout = "e-m:e-Fn32-i64:64-n32:64" target triple = "ppc64le" - define dso_local double @kernel(ptr nocapture noundef readonly %a, ptr nocapture noundef readonly %b, i32 noundef signext %n) local_unnamed_addr { + ; Function Attrs: nofree nosync nounwind memory(argmem: read) uwtable + define dso_local double @kernel(ptr nocapture noundef readonly %a, ptr nocapture noundef readonly %b, i32 noundef signext %n) local_unnamed_addr #0 { entry: - %0 = load double, ptr %a, align 8 - %arrayidx1 = getelementptr inbounds i8, ptr %a, i64 8 - %1 = load double, ptr %arrayidx1, align 8 + %0 = load double, ptr %a, align 8, !tbaa !3 + %arrayidx1 = getelementptr inbounds double, ptr %a, i64 1 + %1 = load double, ptr %arrayidx1, align 8, !tbaa !3 %cmp163 = icmp sgt i32 %n, 0 br i1 %cmp163, label %for.body.preheader, label %for.cond.cleanup for.body.preheader: ; preds = %entry - %wide.trip.count = zext nneg i32 %n to i64 - %scevgep167 = getelementptr i8, ptr %b, i64 -8 + %wide.trip.count = zext i32 %n to i64 + %scevgep1 = getelementptr i8, ptr %b, i64 -8 call void @llvm.set.loop.iterations.i64(i64 %wide.trip.count) br label %for.body @@ -32,11 +43,11 @@ %res.0.lcssa = phi double [ 0.000000e+00, %entry ], [ %30, %for.body ] ret double %res.0.lcssa - for.body: ; preds = %for.body.preheader, %for.body + for.body: ; preds = %for.body, %for.body.preheader %res.0165 = phi double [ 0.000000e+00, %for.body.preheader ], [ %30, %for.body ] - %2 = phi ptr [ %scevgep167, %for.body.preheader ], [ %3, %for.body ] + %2 = phi ptr [ %scevgep1, %for.body.preheader ], [ %3, %for.body ] %3 = getelementptr i8, ptr %2, i64 8 - %4 = load double, ptr %3, align 8 + %4 = load double, ptr %3, align 8, !tbaa !3 %5 = tail call double @llvm.fmuladd.f64(double %0, double %4, double %0) %6 = tail call double @llvm.fmuladd.f64(double %5, double %4, double %5) %7 = tail call double @llvm.fmuladd.f64(double %6, double %4, double %6) @@ -81,23 +92,152 @@ %mul66 = fmul double %12, %mul65 %30 = tail call double @llvm.fmuladd.f64(double %mul66, double %10, double %res.0165) %31 = call i1 @llvm.loop.decrement.i64(i64 1) - br i1 %31, label %for.body, label %for.cond.cleanup + br i1 %31, label %for.body, label %for.cond.cleanup, !llvm.loop !7 } - declare double @llvm.fmuladd.f64(double, double, double) + ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) + declare double @llvm.fmuladd.f64(double, double, double) #1 - declare void @llvm.set.loop.iterations.i64(i64) + ; Function Attrs: nocallback noduplicate nofree nosync nounwind willreturn + declare void @llvm.set.loop.iterations.i64(i64) #2 - declare i1 @llvm.loop.decrement.i64(i64) + ; Function Attrs: nocallback noduplicate nofree nosync nounwind willreturn + declare i1 @llvm.loop.decrement.i64(i64) #2 + attributes #0 = { nofree nosync nounwind memory(argmem: read) uwtable "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crbits,+crypto,+direct-move,+extdiv,+htm,+isa-v206-instructions,+isa-v207-instructions,+isa-v30-instructions,+power8-vector,+power9-vector,+quadword-atomics,+vsx,-aix-small-local-exec-tls,-privileged,-rop-protect,-spe" } + attributes #1 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) } + attributes #2 = { nocallback noduplicate nofree nosync nounwind willreturn } + + !llvm.module.flags = !{!0, !1} + !llvm.ident = !{!2} + + !0 = !{i32 1, !"wchar_size", i32 4} + !1 = !{i32 7, !"uwtable", i32 2} + !2 = !{!"clang version 18.0.0 (https://miratech-soft@dev.azure.com/miratech-soft/llvm/_git/llvm c8d01fb665fc5d9378100a6d92ebcd3be49be655)"} + !3 = !{!4, !4, i64 0} + !4 = !{!"double", !5, i64 0} + !5 = !{!"omnipotent char", !6, i64 0} + !6 = !{!"Simple C/C++ TBAA"} + !7 = distinct !{!7, !8, !9} + !8 = !{!"llvm.loop.mustprogress"} + !9 = !{!"llvm.loop.unroll.disable"} + ... --- name: kernel +alignment: 16 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false tracksRegLiveness: true +hasWinCFI: false +callsEHReturn: false +callsUnwindInit: false +hasEHCatchret: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: vsfrc, preferred-register: '' } + - { id: 1, class: vsfrc, preferred-register: '' } + - { id: 2, class: g8rc, preferred-register: '' } + - { id: 3, class: vsfrc, preferred-register: '' } + - { id: 4, class: vsfrc, preferred-register: '' } + - { id: 5, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 6, class: g8rc, preferred-register: '' } + - { id: 7, class: vsfrc, preferred-register: '' } + - { id: 8, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 9, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 10, class: g8rc, preferred-register: '' } + - { id: 11, class: gprc, preferred-register: '' } + - { id: 12, class: vsfrc, preferred-register: '' } + - { id: 13, class: crrc, preferred-register: '' } + - { id: 14, class: vsfrc, preferred-register: '' } + - { id: 15, class: g8rc, preferred-register: '' } + - { id: 16, class: g8rc, preferred-register: '' } + - { id: 17, class: g8rc, preferred-register: '' } + - { id: 18, class: f8rc, preferred-register: '' } + - { id: 19, class: g8rc_and_g8rc_nox0, preferred-register: '' } + - { id: 20, class: vsfrc, preferred-register: '' } + - { id: 21, class: vsfrc, preferred-register: '' } + - { id: 22, class: vsfrc, preferred-register: '' } + - { id: 23, class: vsfrc, preferred-register: '' } + - { id: 24, class: vsfrc, preferred-register: '' } + - { id: 25, class: vsfrc, preferred-register: '' } + - { id: 26, class: vsfrc, preferred-register: '' } + - { id: 27, class: vsfrc, preferred-register: '' } + - { id: 28, class: vsfrc, preferred-register: '' } + - { id: 29, class: vsfrc, preferred-register: '' } + - { id: 30, class: vsfrc, preferred-register: '' } + - { id: 31, class: vsfrc, preferred-register: '' } + - { id: 32, class: vsfrc, preferred-register: '' } + - { id: 33, class: vsfrc, preferred-register: '' } + - { id: 34, class: vsfrc, preferred-register: '' } + - { id: 35, class: vsfrc, preferred-register: '' } + - { id: 36, class: vsfrc, preferred-register: '' } + - { id: 37, class: vsfrc, preferred-register: '' } + - { id: 38, class: vsfrc, preferred-register: '' } + - { id: 39, class: vsfrc, preferred-register: '' } + - { id: 40, class: vsfrc, preferred-register: '' } + - { id: 41, class: vsfrc, preferred-register: '' } + - { id: 42, class: vsfrc, preferred-register: '' } + - { id: 43, class: vsfrc, preferred-register: '' } + - { id: 44, class: vsfrc, preferred-register: '' } + - { id: 45, class: vsfrc, preferred-register: '' } + - { id: 46, class: vsfrc, preferred-register: '' } + - { id: 47, class: vsfrc, preferred-register: '' } + - { id: 48, class: vsfrc, preferred-register: '' } + - { id: 49, class: vsfrc, preferred-register: '' } + - { id: 50, class: vsfrc, preferred-register: '' } + - { id: 51, class: vsfrc, preferred-register: '' } + - { id: 52, class: vsfrc, preferred-register: '' } + - { id: 53, class: vsfrc, preferred-register: '' } + - { id: 54, class: vsfrc, preferred-register: '' } + - { id: 55, class: vsfrc, preferred-register: '' } + - { id: 56, class: vsfrc, preferred-register: '' } + - { id: 57, class: vsfrc, preferred-register: '' } + - { id: 58, class: vsfrc, preferred-register: '' } + - { id: 59, class: vsfrc, preferred-register: '' } + - { id: 60, class: vsfrc, preferred-register: '' } + - { id: 61, class: vsfrc, preferred-register: '' } + - { id: 62, class: crbitrc, preferred-register: '' } liveins: - { reg: '$x3', virtual-reg: '%8' } - { reg: '$x4', virtual-reg: '%9' } - { reg: '$x5', virtual-reg: '%10' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + localFrameSize: 0 + savePoint: '' + restorePoint: '' +fixedStack: [] +stack: [] +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: {} body: | bb.0.entry: successors: %bb.2(0x50000000), %bb.1(0x30000000) @@ -111,12 +251,16 @@ body: | BCC 44, killed %13, %bb.2 bb.1: + successors: %bb.3(0x80000000) + %12:vsfrc = XXLXORdpz B %bb.3 bb.2.for.body.preheader: - %0:vsfrc = DFLOADf64 0, %8 :: (load (s64) from %ir.a) - %1:vsfrc = DFLOADf64 8, killed %8 :: (load (s64) from %ir.arrayidx1) + successors: %bb.4(0x80000000) + + %0:vsfrc = DFLOADf64 0, %8 :: (load (s64) from %ir.a, !tbaa !3) + %1:vsfrc = DFLOADf64 8, killed %8 :: (load (s64) from %ir.arrayidx1, !tbaa !3) %16:g8rc = IMPLICIT_DEF %15:g8rc = INSERT_SUBREG killed %16, killed %11, %subreg.sub_32 %17:g8rc = RLDICL killed %15, 0, 32 @@ -135,7 +279,7 @@ body: | %4:vsfrc = PHI %14, %bb.2, %7, %bb.4 %5:g8rc_and_g8rc_nox0 = PHI %2, %bb.2, %6, %bb.4 - %18:f8rc, %19:g8rc_and_g8rc_nox0 = LFDU 8, killed %5 :: (load (s64) from %ir.3) + %18:f8rc, %19:g8rc_and_g8rc_nox0 = LFDU 8, killed %5 :: (load (s64) from %ir.3, !tbaa !3) %6:g8rc = COPY killed %19 %20:vsfrc = nofpexcept XSMADDADP %0, %0, %18, implicit $rm %21:vsfrc = nofpexcept XSMADDADP %20, %20, %18, implicit $rm -- cgit v1.1