From 97dd221b6af83d37a4abb1be4f11e7eeec62e363 Mon Sep 17 00:00:00 2001
From: wangpc <wangpengcheng.pp@bytedance.com>
Date: Tue, 23 Jan 2024 16:59:41 +0800
Subject: =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20changes=20intr?=
 =?UTF-8?q?oduced=20through=20rebase?=
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Created using spr 1.3.4

[skip ci]
---
 llvm/test/MC/RISCV/rv32a-invalid.s      |  18 ---
 llvm/test/MC/RISCV/rv32a-valid.s        | 148 -------------------------
 llvm/test/MC/RISCV/rv32zaamo-invalid.s  |  11 ++
 llvm/test/MC/RISCV/rv32zaamo-valid.s    | 122 ++++++++++++++++++++
 llvm/test/MC/RISCV/rv32zalrsc-invalid.s |   7 ++
 llvm/test/MC/RISCV/rv32zalrsc-valid.s   |  36 ++++++
 llvm/test/MC/RISCV/rv64a-invalid.s      |  15 ---
 llvm/test/MC/RISCV/rv64a-valid.s        | 191 --------------------------------
 llvm/test/MC/RISCV/rv64zaamo-invalid.s  |  11 ++
 llvm/test/MC/RISCV/rv64zaamo-valid.s    | 157 ++++++++++++++++++++++++++
 llvm/test/MC/RISCV/rv64zalrsc-invalid.s |   7 ++
 llvm/test/MC/RISCV/rv64zalrsc-valid.s   |  42 +++++++
 12 files changed, 393 insertions(+), 372 deletions(-)
 delete mode 100644 llvm/test/MC/RISCV/rv32a-invalid.s
 delete mode 100644 llvm/test/MC/RISCV/rv32a-valid.s
 create mode 100644 llvm/test/MC/RISCV/rv32zaamo-invalid.s
 create mode 100644 llvm/test/MC/RISCV/rv32zaamo-valid.s
 create mode 100644 llvm/test/MC/RISCV/rv32zalrsc-invalid.s
 create mode 100644 llvm/test/MC/RISCV/rv32zalrsc-valid.s
 delete mode 100644 llvm/test/MC/RISCV/rv64a-invalid.s
 delete mode 100644 llvm/test/MC/RISCV/rv64a-valid.s
 create mode 100644 llvm/test/MC/RISCV/rv64zaamo-invalid.s
 create mode 100644 llvm/test/MC/RISCV/rv64zaamo-valid.s
 create mode 100644 llvm/test/MC/RISCV/rv64zalrsc-invalid.s
 create mode 100644 llvm/test/MC/RISCV/rv64zalrsc-valid.s

diff --git a/llvm/test/MC/RISCV/rv32a-invalid.s b/llvm/test/MC/RISCV/rv32a-invalid.s
deleted file mode 100644
index 34d51fc..0000000
--- a/llvm/test/MC/RISCV/rv32a-invalid.s
+++ /dev/null
@@ -1,18 +0,0 @@
-# RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 | FileCheck %s
-
-# Final operand must have parentheses
-amoswap.w a1, a2, a3 # CHECK: :[[@LINE]]:19: error: expected '(' or optional integer offset
-amomin.w a1, a2, 1 # CHECK: :[[@LINE]]:20: error: expected '(' after optional integer offset
-amomin.w a1, a2, 1(a3) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
-lr.w a4, a5 # CHECK: :[[@LINE]]:10: error: expected '(' or optional integer offset
-
-# Only .aq, .rl, and .aqrl suffixes are valid
-amoxor.w.rlqa a2, a3, (a4) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
-amoor.w.aq.rl a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
-amoor.w. a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
-
-# lr only takes two operands
-lr.w s0, (s1), s2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
-
-# Note: errors for use of RV64A instructions for RV32 are checked in
-# rv64a-valid.s
diff --git a/llvm/test/MC/RISCV/rv32a-valid.s b/llvm/test/MC/RISCV/rv32a-valid.s
deleted file mode 100644
index 1f66680..0000000
--- a/llvm/test/MC/RISCV/rv32a-valid.s
+++ /dev/null
@@ -1,148 +0,0 @@
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+a -riscv-no-aliases -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+a -riscv-no-aliases -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a < %s \
-# RUN:     | llvm-objdump --mattr=+a -M no-aliases -d -r - \
-# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a < %s \
-# RUN:     | llvm-objdump --mattr=+a -M no-aliases -d -r - \
-# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-
-# CHECK-ASM-AND-OBJ: lr.w t0, (t1)
-# CHECK-ASM: encoding: [0xaf,0x22,0x03,0x10]
-lr.w t0, (t1)
-# CHECK-ASM-AND-OBJ: lr.w.aq t1, (t2)
-# CHECK-ASM: encoding: [0x2f,0xa3,0x03,0x14]
-lr.w.aq t1, (t2)
-# CHECK-ASM-AND-OBJ: lr.w.rl t2, (t3)
-# CHECK-ASM: encoding: [0xaf,0x23,0x0e,0x12]
-lr.w.rl t2, (t3)
-# CHECK-ASM-AND-OBJ: lr.w.aqrl t3, (t4)
-# CHECK-ASM: encoding: [0x2f,0xae,0x0e,0x16]
-lr.w.aqrl t3, (t4)
-
-# CHECK-ASM-AND-OBJ: sc.w t6, t5, (t4)
-# CHECK-ASM: encoding: [0xaf,0xaf,0xee,0x19]
-sc.w t6, t5, (t4)
-# CHECK-ASM-AND-OBJ: sc.w.aq t5, t4, (t3)
-# CHECK-ASM: encoding: [0x2f,0x2f,0xde,0x1d]
-sc.w.aq t5, t4, (t3)
-# CHECK-ASM-AND-OBJ: sc.w.rl t4, t3, (t2)
-# CHECK-ASM: encoding: [0xaf,0xae,0xc3,0x1b]
-sc.w.rl t4, t3, (t2)
-# CHECK-ASM-AND-OBJ: sc.w.aqrl t3, t2, (t1)
-# CHECK-ASM: encoding: [0x2f,0x2e,0x73,0x1e]
-sc.w.aqrl t3, t2, (t1)
-
-# CHECK-ASM-AND-OBJ: amoswap.w a4, ra, (s0)
-# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x08]
-amoswap.w a4, ra, (s0)
-# CHECK-ASM-AND-OBJ: amoadd.w a1, a2, (a3)
-# CHECK-ASM: encoding: [0xaf,0xa5,0xc6,0x00]
-amoadd.w a1, a2, (a3)
-# CHECK-ASM-AND-OBJ: amoxor.w a2, a3, (a4)
-# CHECK-ASM: encoding: [0x2f,0x26,0xd7,0x20]
-amoxor.w a2, a3, (a4)
-# CHECK-ASM-AND-OBJ: amoand.w a3, a4, (a5)
-# CHECK-ASM: encoding: [0xaf,0xa6,0xe7,0x60]
-amoand.w a3, a4, (a5)
-# CHECK-ASM-AND-OBJ: amoor.w a4, a5, (a6)
-# CHECK-ASM: encoding: [0x2f,0x27,0xf8,0x40]
-amoor.w a4, a5, (a6)
-# CHECK-ASM-AND-OBJ: amomin.w a5, a6, (a7)
-# CHECK-ASM: encoding: [0xaf,0xa7,0x08,0x81]
-amomin.w a5, a6, (a7)
-# CHECK-ASM-AND-OBJ: amomax.w s7, s6, (s5)
-# CHECK-ASM: encoding: [0xaf,0xab,0x6a,0xa1]
-amomax.w s7, s6, (s5)
-# CHECK-ASM-AND-OBJ: amominu.w s6, s5, (s4)
-# CHECK-ASM: encoding: [0x2f,0x2b,0x5a,0xc1]
-amominu.w s6, s5, (s4)
-# CHECK-ASM-AND-OBJ: amomaxu.w s5, s4, (s3)
-# CHECK-ASM: encoding: [0xaf,0xaa,0x49,0xe1]
-amomaxu.w s5, s4, (s3)
-
-# CHECK-ASM-AND-OBJ: amoswap.w.aq a4, ra, (s0)
-# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x0c]
-amoswap.w.aq a4, ra, (s0)
-# CHECK-ASM-AND-OBJ: amoadd.w.aq a1, a2, (a3)
-# CHECK-ASM: encoding: [0xaf,0xa5,0xc6,0x04]
-amoadd.w.aq a1, a2, (a3)
-# CHECK-ASM-AND-OBJ: amoxor.w.aq a2, a3, (a4)
-# CHECK-ASM: encoding: [0x2f,0x26,0xd7,0x24]
-amoxor.w.aq a2, a3, (a4)
-# CHECK-ASM-AND-OBJ: amoand.w.aq a3, a4, (a5)
-# CHECK-ASM: encoding: [0xaf,0xa6,0xe7,0x64]
-amoand.w.aq a3, a4, (a5)
-# CHECK-ASM-AND-OBJ: amoor.w.aq a4, a5, (a6)
-# CHECK-ASM: encoding: [0x2f,0x27,0xf8,0x44]
-amoor.w.aq a4, a5, (a6)
-# CHECK-ASM-AND-OBJ: amomin.w.aq a5, a6, (a7)
-# CHECK-ASM: encoding: [0xaf,0xa7,0x08,0x85]
-amomin.w.aq a5, a6, (a7)
-# CHECK-ASM-AND-OBJ: amomax.w.aq s7, s6, (s5)
-# CHECK-ASM: encoding: [0xaf,0xab,0x6a,0xa5]
-amomax.w.aq s7, s6, (s5)
-# CHECK-ASM-AND-OBJ: amominu.w.aq s6, s5, (s4)
-# CHECK-ASM: encoding: [0x2f,0x2b,0x5a,0xc5]
-amominu.w.aq s6, s5, (s4)
-# CHECK-ASM-AND-OBJ: amomaxu.w.aq s5, s4, (s3)
-# CHECK-ASM: encoding: [0xaf,0xaa,0x49,0xe5]
-amomaxu.w.aq s5, s4, (s3)
-
-# CHECK-ASM-AND-OBJ: amoswap.w.rl a4, ra, (s0)
-# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x0a]
-amoswap.w.rl a4, ra, (s0)
-# CHECK-ASM-AND-OBJ: amoadd.w.rl a1, a2, (a3)
-# CHECK-ASM: encoding: [0xaf,0xa5,0xc6,0x02]
-amoadd.w.rl a1, a2, (a3)
-# CHECK-ASM-AND-OBJ: amoxor.w.rl a2, a3, (a4)
-# CHECK-ASM: encoding: [0x2f,0x26,0xd7,0x22]
-amoxor.w.rl a2, a3, (a4)
-# CHECK-ASM-AND-OBJ: amoand.w.rl a3, a4, (a5)
-# CHECK-ASM: encoding: [0xaf,0xa6,0xe7,0x62]
-amoand.w.rl a3, a4, (a5)
-# CHECK-ASM-AND-OBJ: amoor.w.rl a4, a5, (a6)
-# CHECK-ASM: encoding: [0x2f,0x27,0xf8,0x42]
-amoor.w.rl a4, a5, (a6)
-# CHECK-ASM-AND-OBJ: amomin.w.rl a5, a6, (a7)
-# CHECK-ASM: encoding: [0xaf,0xa7,0x08,0x83]
-amomin.w.rl a5, a6, (a7)
-# CHECK-ASM-AND-OBJ: amomax.w.rl s7, s6, (s5)
-# CHECK-ASM: encoding: [0xaf,0xab,0x6a,0xa3]
-amomax.w.rl s7, s6, (s5)
-# CHECK-ASM-AND-OBJ: amominu.w.rl s6, s5, (s4)
-# CHECK-ASM: encoding: [0x2f,0x2b,0x5a,0xc3]
-amominu.w.rl s6, s5, (s4)
-# CHECK-ASM-AND-OBJ: amomaxu.w.rl s5, s4, (s3)
-# CHECK-ASM: encoding: [0xaf,0xaa,0x49,0xe3]
-amomaxu.w.rl s5, s4, (s3)
-
-# CHECK-ASM-AND-OBJ: amoswap.w.aqrl a4, ra, (s0)
-# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x0e]
-amoswap.w.aqrl a4, ra, (s0)
-# CHECK-ASM-AND-OBJ: amoadd.w.aqrl a1, a2, (a3)
-# CHECK-ASM: encoding: [0xaf,0xa5,0xc6,0x06]
-amoadd.w.aqrl a1, a2, (a3)
-# CHECK-ASM-AND-OBJ: amoxor.w.aqrl a2, a3, (a4)
-# CHECK-ASM: encoding: [0x2f,0x26,0xd7,0x26]
-amoxor.w.aqrl a2, a3, (a4)
-# CHECK-ASM-AND-OBJ: amoand.w.aqrl a3, a4, (a5)
-# CHECK-ASM: encoding: [0xaf,0xa6,0xe7,0x66]
-amoand.w.aqrl a3, a4, (a5)
-# CHECK-ASM-AND-OBJ: amoor.w.aqrl a4, a5, (a6)
-# CHECK-ASM: encoding: [0x2f,0x27,0xf8,0x46]
-amoor.w.aqrl a4, a5, (a6)
-# CHECK-ASM-AND-OBJ: amomin.w.aqrl a5, a6, (a7)
-# CHECK-ASM: encoding: [0xaf,0xa7,0x08,0x87]
-amomin.w.aqrl a5, a6, (a7)
-# CHECK-ASM-AND-OBJ: amomax.w.aqrl s7, s6, (s5)
-# CHECK-ASM: encoding: [0xaf,0xab,0x6a,0xa7]
-amomax.w.aqrl s7, s6, (s5)
-# CHECK-ASM-AND-OBJ: amominu.w.aqrl s6, s5, (s4)
-# CHECK-ASM: encoding: [0x2f,0x2b,0x5a,0xc7]
-amominu.w.aqrl s6, s5, (s4)
-# CHECK-ASM-AND-OBJ: amomaxu.w.aqrl s5, s4, (s3)
-# CHECK-ASM: encoding: [0xaf,0xaa,0x49,0xe7]
-amomaxu.w.aqrl s5, s4, (s3)
diff --git a/llvm/test/MC/RISCV/rv32zaamo-invalid.s b/llvm/test/MC/RISCV/rv32zaamo-invalid.s
new file mode 100644
index 0000000..f6183fb
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zaamo-invalid.s
@@ -0,0 +1,11 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 | FileCheck %s
+
+# Final operand must have parentheses
+amoswap.w a1, a2, a3 # CHECK: :[[@LINE]]:19: error: expected '(' or optional integer offset
+amomin.w a1, a2, 1 # CHECK: :[[@LINE]]:20: error: expected '(' after optional integer offset
+amomin.w a1, a2, 1(a3) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
+
+# Only .aq, .rl, and .aqrl suffixes are valid
+amoxor.w.rlqa a2, a3, (a4) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
+amoor.w.aq.rl a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
+amoor.w. a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
diff --git a/llvm/test/MC/RISCV/rv32zaamo-valid.s b/llvm/test/MC/RISCV/rv32zaamo-valid.s
new file mode 100644
index 0000000..ea1ae79
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zaamo-valid.s
@@ -0,0 +1,122 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+a -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+a -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a < %s \
+# RUN:     | llvm-objdump --mattr=+a -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a < %s \
+# RUN:     | llvm-objdump --mattr=+a -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: amoswap.w a4, ra, (s0)
+# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x08]
+amoswap.w a4, ra, (s0)
+# CHECK-ASM-AND-OBJ: amoadd.w a1, a2, (a3)
+# CHECK-ASM: encoding: [0xaf,0xa5,0xc6,0x00]
+amoadd.w a1, a2, (a3)
+# CHECK-ASM-AND-OBJ: amoxor.w a2, a3, (a4)
+# CHECK-ASM: encoding: [0x2f,0x26,0xd7,0x20]
+amoxor.w a2, a3, (a4)
+# CHECK-ASM-AND-OBJ: amoand.w a3, a4, (a5)
+# CHECK-ASM: encoding: [0xaf,0xa6,0xe7,0x60]
+amoand.w a3, a4, (a5)
+# CHECK-ASM-AND-OBJ: amoor.w a4, a5, (a6)
+# CHECK-ASM: encoding: [0x2f,0x27,0xf8,0x40]
+amoor.w a4, a5, (a6)
+# CHECK-ASM-AND-OBJ: amomin.w a5, a6, (a7)
+# CHECK-ASM: encoding: [0xaf,0xa7,0x08,0x81]
+amomin.w a5, a6, (a7)
+# CHECK-ASM-AND-OBJ: amomax.w s7, s6, (s5)
+# CHECK-ASM: encoding: [0xaf,0xab,0x6a,0xa1]
+amomax.w s7, s6, (s5)
+# CHECK-ASM-AND-OBJ: amominu.w s6, s5, (s4)
+# CHECK-ASM: encoding: [0x2f,0x2b,0x5a,0xc1]
+amominu.w s6, s5, (s4)
+# CHECK-ASM-AND-OBJ: amomaxu.w s5, s4, (s3)
+# CHECK-ASM: encoding: [0xaf,0xaa,0x49,0xe1]
+amomaxu.w s5, s4, (s3)
+
+# CHECK-ASM-AND-OBJ: amoswap.w.aq a4, ra, (s0)
+# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x0c]
+amoswap.w.aq a4, ra, (s0)
+# CHECK-ASM-AND-OBJ: amoadd.w.aq a1, a2, (a3)
+# CHECK-ASM: encoding: [0xaf,0xa5,0xc6,0x04]
+amoadd.w.aq a1, a2, (a3)
+# CHECK-ASM-AND-OBJ: amoxor.w.aq a2, a3, (a4)
+# CHECK-ASM: encoding: [0x2f,0x26,0xd7,0x24]
+amoxor.w.aq a2, a3, (a4)
+# CHECK-ASM-AND-OBJ: amoand.w.aq a3, a4, (a5)
+# CHECK-ASM: encoding: [0xaf,0xa6,0xe7,0x64]
+amoand.w.aq a3, a4, (a5)
+# CHECK-ASM-AND-OBJ: amoor.w.aq a4, a5, (a6)
+# CHECK-ASM: encoding: [0x2f,0x27,0xf8,0x44]
+amoor.w.aq a4, a5, (a6)
+# CHECK-ASM-AND-OBJ: amomin.w.aq a5, a6, (a7)
+# CHECK-ASM: encoding: [0xaf,0xa7,0x08,0x85]
+amomin.w.aq a5, a6, (a7)
+# CHECK-ASM-AND-OBJ: amomax.w.aq s7, s6, (s5)
+# CHECK-ASM: encoding: [0xaf,0xab,0x6a,0xa5]
+amomax.w.aq s7, s6, (s5)
+# CHECK-ASM-AND-OBJ: amominu.w.aq s6, s5, (s4)
+# CHECK-ASM: encoding: [0x2f,0x2b,0x5a,0xc5]
+amominu.w.aq s6, s5, (s4)
+# CHECK-ASM-AND-OBJ: amomaxu.w.aq s5, s4, (s3)
+# CHECK-ASM: encoding: [0xaf,0xaa,0x49,0xe5]
+amomaxu.w.aq s5, s4, (s3)
+
+# CHECK-ASM-AND-OBJ: amoswap.w.rl a4, ra, (s0)
+# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x0a]
+amoswap.w.rl a4, ra, (s0)
+# CHECK-ASM-AND-OBJ: amoadd.w.rl a1, a2, (a3)
+# CHECK-ASM: encoding: [0xaf,0xa5,0xc6,0x02]
+amoadd.w.rl a1, a2, (a3)
+# CHECK-ASM-AND-OBJ: amoxor.w.rl a2, a3, (a4)
+# CHECK-ASM: encoding: [0x2f,0x26,0xd7,0x22]
+amoxor.w.rl a2, a3, (a4)
+# CHECK-ASM-AND-OBJ: amoand.w.rl a3, a4, (a5)
+# CHECK-ASM: encoding: [0xaf,0xa6,0xe7,0x62]
+amoand.w.rl a3, a4, (a5)
+# CHECK-ASM-AND-OBJ: amoor.w.rl a4, a5, (a6)
+# CHECK-ASM: encoding: [0x2f,0x27,0xf8,0x42]
+amoor.w.rl a4, a5, (a6)
+# CHECK-ASM-AND-OBJ: amomin.w.rl a5, a6, (a7)
+# CHECK-ASM: encoding: [0xaf,0xa7,0x08,0x83]
+amomin.w.rl a5, a6, (a7)
+# CHECK-ASM-AND-OBJ: amomax.w.rl s7, s6, (s5)
+# CHECK-ASM: encoding: [0xaf,0xab,0x6a,0xa3]
+amomax.w.rl s7, s6, (s5)
+# CHECK-ASM-AND-OBJ: amominu.w.rl s6, s5, (s4)
+# CHECK-ASM: encoding: [0x2f,0x2b,0x5a,0xc3]
+amominu.w.rl s6, s5, (s4)
+# CHECK-ASM-AND-OBJ: amomaxu.w.rl s5, s4, (s3)
+# CHECK-ASM: encoding: [0xaf,0xaa,0x49,0xe3]
+amomaxu.w.rl s5, s4, (s3)
+
+# CHECK-ASM-AND-OBJ: amoswap.w.aqrl a4, ra, (s0)
+# CHECK-ASM: encoding: [0x2f,0x27,0x14,0x0e]
+amoswap.w.aqrl a4, ra, (s0)
+# CHECK-ASM-AND-OBJ: amoadd.w.aqrl a1, a2, (a3)
+# CHECK-ASM: encoding: [0xaf,0xa5,0xc6,0x06]
+amoadd.w.aqrl a1, a2, (a3)
+# CHECK-ASM-AND-OBJ: amoxor.w.aqrl a2, a3, (a4)
+# CHECK-ASM: encoding: [0x2f,0x26,0xd7,0x26]
+amoxor.w.aqrl a2, a3, (a4)
+# CHECK-ASM-AND-OBJ: amoand.w.aqrl a3, a4, (a5)
+# CHECK-ASM: encoding: [0xaf,0xa6,0xe7,0x66]
+amoand.w.aqrl a3, a4, (a5)
+# CHECK-ASM-AND-OBJ: amoor.w.aqrl a4, a5, (a6)
+# CHECK-ASM: encoding: [0x2f,0x27,0xf8,0x46]
+amoor.w.aqrl a4, a5, (a6)
+# CHECK-ASM-AND-OBJ: amomin.w.aqrl a5, a6, (a7)
+# CHECK-ASM: encoding: [0xaf,0xa7,0x08,0x87]
+amomin.w.aqrl a5, a6, (a7)
+# CHECK-ASM-AND-OBJ: amomax.w.aqrl s7, s6, (s5)
+# CHECK-ASM: encoding: [0xaf,0xab,0x6a,0xa7]
+amomax.w.aqrl s7, s6, (s5)
+# CHECK-ASM-AND-OBJ: amominu.w.aqrl s6, s5, (s4)
+# CHECK-ASM: encoding: [0x2f,0x2b,0x5a,0xc7]
+amominu.w.aqrl s6, s5, (s4)
+# CHECK-ASM-AND-OBJ: amomaxu.w.aqrl s5, s4, (s3)
+# CHECK-ASM: encoding: [0xaf,0xaa,0x49,0xe7]
+amomaxu.w.aqrl s5, s4, (s3)
diff --git a/llvm/test/MC/RISCV/rv32zalrsc-invalid.s b/llvm/test/MC/RISCV/rv32zalrsc-invalid.s
new file mode 100644
index 0000000..61cfc61
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zalrsc-invalid.s
@@ -0,0 +1,7 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 | FileCheck %s
+
+# Final operand must have parentheses
+lr.w a4, a5 # CHECK: :[[@LINE]]:10: error: expected '(' or optional integer offset
+
+# lr only takes two operands
+lr.w s0, (s1), s2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv32zalrsc-valid.s b/llvm/test/MC/RISCV/rv32zalrsc-valid.s
new file mode 100644
index 0000000..0d4881a
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv32zalrsc-valid.s
@@ -0,0 +1,36 @@
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+a -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+a -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a < %s \
+# RUN:     | llvm-objdump --mattr=+a -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a < %s \
+# RUN:     | llvm-objdump --mattr=+a -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+
+# CHECK-ASM-AND-OBJ: lr.w t0, (t1)
+# CHECK-ASM: encoding: [0xaf,0x22,0x03,0x10]
+lr.w t0, (t1)
+# CHECK-ASM-AND-OBJ: lr.w.aq t1, (t2)
+# CHECK-ASM: encoding: [0x2f,0xa3,0x03,0x14]
+lr.w.aq t1, (t2)
+# CHECK-ASM-AND-OBJ: lr.w.rl t2, (t3)
+# CHECK-ASM: encoding: [0xaf,0x23,0x0e,0x12]
+lr.w.rl t2, (t3)
+# CHECK-ASM-AND-OBJ: lr.w.aqrl t3, (t4)
+# CHECK-ASM: encoding: [0x2f,0xae,0x0e,0x16]
+lr.w.aqrl t3, (t4)
+
+# CHECK-ASM-AND-OBJ: sc.w t6, t5, (t4)
+# CHECK-ASM: encoding: [0xaf,0xaf,0xee,0x19]
+sc.w t6, t5, (t4)
+# CHECK-ASM-AND-OBJ: sc.w.aq t5, t4, (t3)
+# CHECK-ASM: encoding: [0x2f,0x2f,0xde,0x1d]
+sc.w.aq t5, t4, (t3)
+# CHECK-ASM-AND-OBJ: sc.w.rl t4, t3, (t2)
+# CHECK-ASM: encoding: [0xaf,0xae,0xc3,0x1b]
+sc.w.rl t4, t3, (t2)
+# CHECK-ASM-AND-OBJ: sc.w.aqrl t3, t2, (t1)
+# CHECK-ASM: encoding: [0x2f,0x2e,0x73,0x1e]
+sc.w.aqrl t3, t2, (t1)
diff --git a/llvm/test/MC/RISCV/rv64a-invalid.s b/llvm/test/MC/RISCV/rv64a-invalid.s
deleted file mode 100644
index 2816f43..0000000
--- a/llvm/test/MC/RISCV/rv64a-invalid.s
+++ /dev/null
@@ -1,15 +0,0 @@
-# RUN: not llvm-mc -triple riscv64 -mattr=+a < %s 2>&1 | FileCheck %s
-
-# Final operand must have parentheses
-amoswap.d a1, a2, a3 # CHECK: :[[@LINE]]:19: error: expected '(' or optional integer offset
-amomin.d a1, a2, 1 # CHECK: :[[@LINE]]:20: error: expected '(' after optional integer offset
-amomin.d a1, a2, 1(a3) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
-lr.d a4, a5 # CHECK: :[[@LINE]]:10: error: expected '(' or optional integer offset
-
-# Only .aq, .rl, and .aqrl suffixes are valid
-amoxor.d.rlqa a2, a3, (a4) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
-amoor.d.aq.rl a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
-amoor.d. a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
-
-# lr only takes two operands
-lr.d s0, (s1), s2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv64a-valid.s b/llvm/test/MC/RISCV/rv64a-valid.s
deleted file mode 100644
index 3276b39..0000000
--- a/llvm/test/MC/RISCV/rv64a-valid.s
+++ /dev/null
@@ -1,191 +0,0 @@
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+a -riscv-no-aliases -show-encoding \
-# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a < %s \
-# RUN:     | llvm-objdump --mattr=+a -M no-aliases -d -r - \
-# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
-#
-# RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 \
-# RUN:     | FileCheck -check-prefix=CHECK-RV32 %s
-
-# CHECK-ASM-AND-OBJ: lr.d t0, (t1)
-# CHECK-ASM: encoding: [0xaf,0x32,0x03,0x10]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-lr.d t0, (t1)
-# CHECK-ASM-AND-OBJ: lr.d.aq t1, (t2)
-# CHECK-ASM: encoding: [0x2f,0xb3,0x03,0x14]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-lr.d.aq t1, (t2)
-# CHECK-ASM-AND-OBJ: lr.d.rl t2, (t3)
-# CHECK-ASM: encoding: [0xaf,0x33,0x0e,0x12]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-lr.d.rl t2, (t3)
-# CHECK-ASM-AND-OBJ: lr.d.aqrl t3, (t4)
-# CHECK-ASM: encoding: [0x2f,0xbe,0x0e,0x16]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-lr.d.aqrl t3, (t4)
-
-# CHECK-ASM-AND-OBJ: sc.d t6, t5, (t4)
-# CHECK-ASM: encoding: [0xaf,0xbf,0xee,0x19]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-sc.d t6, t5, (t4)
-# CHECK-ASM-AND-OBJ: sc.d.aq t5, t4, (t3)
-# CHECK-ASM: encoding: [0x2f,0x3f,0xde,0x1d]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-sc.d.aq t5, t4, (t3)
-# CHECK-ASM-AND-OBJ: sc.d.rl t4, t3, (t2)
-# CHECK-ASM: encoding: [0xaf,0xbe,0xc3,0x1b]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-sc.d.rl t4, t3, (t2)
-# CHECK-ASM-AND-OBJ: sc.d.aqrl t3, t2, (t1)
-# CHECK-ASM: encoding: [0x2f,0x3e,0x73,0x1e]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-sc.d.aqrl t3, t2, (t1)
-
-# CHECK-ASM-AND-OBJ: amoswap.d a4, ra, (s0)
-# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x08]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amoswap.d a4, ra, (s0)
-# CHECK-ASM-AND-OBJ: amoadd.d a1, a2, (a3)
-# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x00]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amoadd.d a1, a2, (a3)
-# CHECK-ASM-AND-OBJ: amoxor.d a2, a3, (a4)
-# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x20]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amoxor.d a2, a3, (a4)
-# CHECK-ASM-AND-OBJ: amoand.d a3, a4, (a5)
-# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x60]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amoand.d a3, a4, (a5)
-# CHECK-ASM-AND-OBJ: amoor.d a4, a5, (a6)
-# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x40]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amoor.d a4, a5, (a6)
-# CHECK-ASM-AND-OBJ: amomin.d a5, a6, (a7)
-# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x81]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amomin.d a5, a6, (a7)
-# CHECK-ASM-AND-OBJ: amomax.d s7, s6, (s5)
-# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa1]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amomax.d s7, s6, (s5)
-# CHECK-ASM-AND-OBJ: amominu.d s6, s5, (s4)
-# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc1]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amominu.d s6, s5, (s4)
-# CHECK-ASM-AND-OBJ: amomaxu.d s5, s4, (s3)
-# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe1]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amomaxu.d s5, s4, (s3)
-
-
-# CHECK-ASM-AND-OBJ: amoswap.d.aq a4, ra, (s0)
-# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0c]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amoswap.d.aq a4, ra, (s0)
-# CHECK-ASM-AND-OBJ: amoadd.d.aq a1, a2, (a3)
-# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x04]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amoadd.d.aq a1, a2, (a3)
-# CHECK-ASM-AND-OBJ: amoxor.d.aq a2, a3, (a4)
-# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x24]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amoxor.d.aq a2, a3, (a4)
-# CHECK-ASM-AND-OBJ: amoand.d.aq a3, a4, (a5)
-# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x64]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amoand.d.aq a3, a4, (a5)
-# CHECK-ASM-AND-OBJ: amoor.d.aq a4, a5, (a6)
-# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x44]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amoor.d.aq a4, a5, (a6)
-# CHECK-ASM-AND-OBJ: amomin.d.aq a5, a6, (a7)
-# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x85]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amomin.d.aq a5, a6, (a7)
-# CHECK-ASM-AND-OBJ: amomax.d.aq s7, s6, (s5)
-# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa5]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amomax.d.aq s7, s6, (s5)
-# CHECK-ASM-AND-OBJ: amominu.d.aq s6, s5, (s4)
-# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc5]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amominu.d.aq s6, s5, (s4)
-# CHECK-ASM-AND-OBJ: amomaxu.d.aq s5, s4, (s3)
-# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe5]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amomaxu.d.aq s5, s4, (s3)
-
-# CHECK-ASM-AND-OBJ: amoswap.d.rl a4, ra, (s0)
-# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0a]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amoswap.d.rl a4, ra, (s0)
-# CHECK-ASM-AND-OBJ: amoadd.d.rl a1, a2, (a3)
-# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x02]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amoadd.d.rl a1, a2, (a3)
-# CHECK-ASM-AND-OBJ: amoxor.d.rl a2, a3, (a4)
-# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x22]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amoxor.d.rl a2, a3, (a4)
-# CHECK-ASM-AND-OBJ: amoand.d.rl a3, a4, (a5)
-# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x62]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amoand.d.rl a3, a4, (a5)
-# CHECK-ASM-AND-OBJ: amoor.d.rl a4, a5, (a6)
-# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x42]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amoor.d.rl a4, a5, (a6)
-# CHECK-ASM-AND-OBJ: amomin.d.rl a5, a6, (a7)
-# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x83]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amomin.d.rl a5, a6, (a7)
-# CHECK-ASM-AND-OBJ: amomax.d.rl s7, s6, (s5)
-# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa3]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amomax.d.rl s7, s6, (s5)
-# CHECK-ASM-AND-OBJ: amominu.d.rl s6, s5, (s4)
-# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc3]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amominu.d.rl s6, s5, (s4)
-# CHECK-ASM-AND-OBJ: amomaxu.d.rl s5, s4, (s3)
-# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe3]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amomaxu.d.rl s5, s4, (s3)
-
-# CHECK-ASM-AND-OBJ: amoswap.d.aqrl a4, ra, (s0)
-# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0e]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amoswap.d.aqrl a4, ra, (s0)
-# CHECK-ASM-AND-OBJ: amoadd.d.aqrl a1, a2, (a3)
-# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x06]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amoadd.d.aqrl a1, a2, (a3)
-# CHECK-ASM-AND-OBJ: amoxor.d.aqrl a2, a3, (a4)
-# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x26]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amoxor.d.aqrl a2, a3, (a4)
-# CHECK-ASM-AND-OBJ: amoand.d.aqrl a3, a4, (a5)
-# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x66]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amoand.d.aqrl a3, a4, (a5)
-# CHECK-ASM-AND-OBJ: amoor.d.aqrl a4, a5, (a6)
-# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x46]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amoor.d.aqrl a4, a5, (a6)
-# CHECK-ASM-AND-OBJ: amomin.d.aqrl a5, a6, (a7)
-# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x87]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amomin.d.aqrl a5, a6, (a7)
-# CHECK-ASM-AND-OBJ: amomax.d.aqrl s7, s6, (s5)
-# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa7]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amomax.d.aqrl s7, s6, (s5)
-# CHECK-ASM-AND-OBJ: amominu.d.aqrl s6, s5, (s4)
-# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc7]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amominu.d.aqrl s6, s5, (s4)
-# CHECK-ASM-AND-OBJ: amomaxu.d.aqrl s5, s4, (s3)
-# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe7]
-# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
-amomaxu.d.aqrl s5, s4, (s3)
diff --git a/llvm/test/MC/RISCV/rv64zaamo-invalid.s b/llvm/test/MC/RISCV/rv64zaamo-invalid.s
new file mode 100644
index 0000000..70a4e55
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zaamo-invalid.s
@@ -0,0 +1,11 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+a < %s 2>&1 | FileCheck %s
+
+# Final operand must have parentheses
+amoswap.d a1, a2, a3 # CHECK: :[[@LINE]]:19: error: expected '(' or optional integer offset
+amomin.d a1, a2, 1 # CHECK: :[[@LINE]]:20: error: expected '(' after optional integer offset
+amomin.d a1, a2, 1(a3) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0
+
+# Only .aq, .rl, and .aqrl suffixes are valid
+amoxor.d.rlqa a2, a3, (a4) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
+amoor.d.aq.rl a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
+amoor.d. a4, a5, (a6) # CHECK: :[[@LINE]]:1: error: unrecognized instruction mnemonic
diff --git a/llvm/test/MC/RISCV/rv64zaamo-valid.s b/llvm/test/MC/RISCV/rv64zaamo-valid.s
new file mode 100644
index 0000000..73cdc55
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zaamo-valid.s
@@ -0,0 +1,157 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+a -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a < %s \
+# RUN:     | llvm-objdump --mattr=+a -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 \
+# RUN:     | FileCheck -check-prefix=CHECK-RV32 %s
+
+# CHECK-ASM-AND-OBJ: amoswap.d a4, ra, (s0)
+# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x08]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoswap.d a4, ra, (s0)
+# CHECK-ASM-AND-OBJ: amoadd.d a1, a2, (a3)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x00]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoadd.d a1, a2, (a3)
+# CHECK-ASM-AND-OBJ: amoxor.d a2, a3, (a4)
+# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x20]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoxor.d a2, a3, (a4)
+# CHECK-ASM-AND-OBJ: amoand.d a3, a4, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x60]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoand.d a3, a4, (a5)
+# CHECK-ASM-AND-OBJ: amoor.d a4, a5, (a6)
+# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x40]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoor.d a4, a5, (a6)
+# CHECK-ASM-AND-OBJ: amomin.d a5, a6, (a7)
+# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x81]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amomin.d a5, a6, (a7)
+# CHECK-ASM-AND-OBJ: amomax.d s7, s6, (s5)
+# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa1]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amomax.d s7, s6, (s5)
+# CHECK-ASM-AND-OBJ: amominu.d s6, s5, (s4)
+# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc1]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amominu.d s6, s5, (s4)
+# CHECK-ASM-AND-OBJ: amomaxu.d s5, s4, (s3)
+# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe1]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amomaxu.d s5, s4, (s3)
+
+
+# CHECK-ASM-AND-OBJ: amoswap.d.aq a4, ra, (s0)
+# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0c]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoswap.d.aq a4, ra, (s0)
+# CHECK-ASM-AND-OBJ: amoadd.d.aq a1, a2, (a3)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x04]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoadd.d.aq a1, a2, (a3)
+# CHECK-ASM-AND-OBJ: amoxor.d.aq a2, a3, (a4)
+# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x24]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoxor.d.aq a2, a3, (a4)
+# CHECK-ASM-AND-OBJ: amoand.d.aq a3, a4, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x64]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoand.d.aq a3, a4, (a5)
+# CHECK-ASM-AND-OBJ: amoor.d.aq a4, a5, (a6)
+# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x44]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoor.d.aq a4, a5, (a6)
+# CHECK-ASM-AND-OBJ: amomin.d.aq a5, a6, (a7)
+# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x85]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amomin.d.aq a5, a6, (a7)
+# CHECK-ASM-AND-OBJ: amomax.d.aq s7, s6, (s5)
+# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa5]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amomax.d.aq s7, s6, (s5)
+# CHECK-ASM-AND-OBJ: amominu.d.aq s6, s5, (s4)
+# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc5]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amominu.d.aq s6, s5, (s4)
+# CHECK-ASM-AND-OBJ: amomaxu.d.aq s5, s4, (s3)
+# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe5]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amomaxu.d.aq s5, s4, (s3)
+
+# CHECK-ASM-AND-OBJ: amoswap.d.rl a4, ra, (s0)
+# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0a]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoswap.d.rl a4, ra, (s0)
+# CHECK-ASM-AND-OBJ: amoadd.d.rl a1, a2, (a3)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x02]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoadd.d.rl a1, a2, (a3)
+# CHECK-ASM-AND-OBJ: amoxor.d.rl a2, a3, (a4)
+# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x22]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoxor.d.rl a2, a3, (a4)
+# CHECK-ASM-AND-OBJ: amoand.d.rl a3, a4, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x62]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoand.d.rl a3, a4, (a5)
+# CHECK-ASM-AND-OBJ: amoor.d.rl a4, a5, (a6)
+# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x42]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoor.d.rl a4, a5, (a6)
+# CHECK-ASM-AND-OBJ: amomin.d.rl a5, a6, (a7)
+# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x83]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amomin.d.rl a5, a6, (a7)
+# CHECK-ASM-AND-OBJ: amomax.d.rl s7, s6, (s5)
+# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa3]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amomax.d.rl s7, s6, (s5)
+# CHECK-ASM-AND-OBJ: amominu.d.rl s6, s5, (s4)
+# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc3]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amominu.d.rl s6, s5, (s4)
+# CHECK-ASM-AND-OBJ: amomaxu.d.rl s5, s4, (s3)
+# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe3]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amomaxu.d.rl s5, s4, (s3)
+
+# CHECK-ASM-AND-OBJ: amoswap.d.aqrl a4, ra, (s0)
+# CHECK-ASM: encoding: [0x2f,0x37,0x14,0x0e]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoswap.d.aqrl a4, ra, (s0)
+# CHECK-ASM-AND-OBJ: amoadd.d.aqrl a1, a2, (a3)
+# CHECK-ASM: encoding: [0xaf,0xb5,0xc6,0x06]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoadd.d.aqrl a1, a2, (a3)
+# CHECK-ASM-AND-OBJ: amoxor.d.aqrl a2, a3, (a4)
+# CHECK-ASM: encoding: [0x2f,0x36,0xd7,0x26]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoxor.d.aqrl a2, a3, (a4)
+# CHECK-ASM-AND-OBJ: amoand.d.aqrl a3, a4, (a5)
+# CHECK-ASM: encoding: [0xaf,0xb6,0xe7,0x66]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoand.d.aqrl a3, a4, (a5)
+# CHECK-ASM-AND-OBJ: amoor.d.aqrl a4, a5, (a6)
+# CHECK-ASM: encoding: [0x2f,0x37,0xf8,0x46]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amoor.d.aqrl a4, a5, (a6)
+# CHECK-ASM-AND-OBJ: amomin.d.aqrl a5, a6, (a7)
+# CHECK-ASM: encoding: [0xaf,0xb7,0x08,0x87]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amomin.d.aqrl a5, a6, (a7)
+# CHECK-ASM-AND-OBJ: amomax.d.aqrl s7, s6, (s5)
+# CHECK-ASM: encoding: [0xaf,0xbb,0x6a,0xa7]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amomax.d.aqrl s7, s6, (s5)
+# CHECK-ASM-AND-OBJ: amominu.d.aqrl s6, s5, (s4)
+# CHECK-ASM: encoding: [0x2f,0x3b,0x5a,0xc7]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amominu.d.aqrl s6, s5, (s4)
+# CHECK-ASM-AND-OBJ: amomaxu.d.aqrl s5, s4, (s3)
+# CHECK-ASM: encoding: [0xaf,0xba,0x49,0xe7]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+amomaxu.d.aqrl s5, s4, (s3)
diff --git a/llvm/test/MC/RISCV/rv64zalrsc-invalid.s b/llvm/test/MC/RISCV/rv64zalrsc-invalid.s
new file mode 100644
index 0000000..0be0097
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zalrsc-invalid.s
@@ -0,0 +1,7 @@
+# RUN: not llvm-mc -triple riscv64 -mattr=+a < %s 2>&1 | FileCheck %s
+
+# Final operand must have parentheses
+lr.d a4, a5 # CHECK: :[[@LINE]]:10: error: expected '(' or optional integer offset
+
+# lr only takes two operands
+lr.d s0, (s1), s2 # CHECK: :[[@LINE]]:16: error: invalid operand for instruction
diff --git a/llvm/test/MC/RISCV/rv64zalrsc-valid.s b/llvm/test/MC/RISCV/rv64zalrsc-valid.s
new file mode 100644
index 0000000..d4c8752
--- /dev/null
+++ b/llvm/test/MC/RISCV/rv64zalrsc-valid.s
@@ -0,0 +1,42 @@
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+a -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a < %s \
+# RUN:     | llvm-objdump --mattr=+a -M no-aliases -d -r - \
+# RUN:     | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
+#
+# RUN: not llvm-mc -triple riscv32 -mattr=+a < %s 2>&1 \
+# RUN:     | FileCheck -check-prefix=CHECK-RV32 %s
+
+# CHECK-ASM-AND-OBJ: lr.d t0, (t1)
+# CHECK-ASM: encoding: [0xaf,0x32,0x03,0x10]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+lr.d t0, (t1)
+# CHECK-ASM-AND-OBJ: lr.d.aq t1, (t2)
+# CHECK-ASM: encoding: [0x2f,0xb3,0x03,0x14]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+lr.d.aq t1, (t2)
+# CHECK-ASM-AND-OBJ: lr.d.rl t2, (t3)
+# CHECK-ASM: encoding: [0xaf,0x33,0x0e,0x12]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+lr.d.rl t2, (t3)
+# CHECK-ASM-AND-OBJ: lr.d.aqrl t3, (t4)
+# CHECK-ASM: encoding: [0x2f,0xbe,0x0e,0x16]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+lr.d.aqrl t3, (t4)
+
+# CHECK-ASM-AND-OBJ: sc.d t6, t5, (t4)
+# CHECK-ASM: encoding: [0xaf,0xbf,0xee,0x19]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+sc.d t6, t5, (t4)
+# CHECK-ASM-AND-OBJ: sc.d.aq t5, t4, (t3)
+# CHECK-ASM: encoding: [0x2f,0x3f,0xde,0x1d]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+sc.d.aq t5, t4, (t3)
+# CHECK-ASM-AND-OBJ: sc.d.rl t4, t3, (t2)
+# CHECK-ASM: encoding: [0xaf,0xbe,0xc3,0x1b]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+sc.d.rl t4, t3, (t2)
+# CHECK-ASM-AND-OBJ: sc.d.aqrl t3, t2, (t1)
+# CHECK-ASM: encoding: [0x2f,0x3e,0x73,0x1e]
+# CHECK-RV32: :[[@LINE+1]]:1: error: instruction requires the following: RV64I Base Instruction Set{{$}}
+sc.d.aqrl t3, t2, (t1)
-- 
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