From 1254c70db9559d0c7cbcfa98d046120bd15f2a29 Mon Sep 17 00:00:00 2001
From: Tom Stellard <tstellar@redhat.com>
Date: Tue, 28 Nov 2017 22:02:15 +0000
Subject: Merging r316035:

------------------------------------------------------------------------
r316035 | tnorthover | 2017-10-17 14:43:52 -0700 (Tue, 17 Oct 2017) | 6 lines

AArch64: account for possible frame index operand in compares.

If the address of a local is used in a comparison, AArch64 can fold the
address-calculation into the comparison via "adds". Unfortunately, a couple of
places (both hit in this one test) are not ready to deal with that yet and just
assume the first source operand is a register.
------------------------------------------------------------------------

llvm-svn: 319231
---
 llvm/lib/Target/AArch64/AArch64InstrInfo.cpp          |  6 ++++++
 .../AArch64/AArch64RedundantCopyElimination.cpp       |  3 +++
 llvm/test/CodeGen/AArch64/cmp-frameindex.ll           | 19 +++++++++++++++++++
 3 files changed, 28 insertions(+)
 create mode 100644 llvm/test/CodeGen/AArch64/cmp-frameindex.ll

diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index c0c6055..13c80a4 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -940,6 +940,12 @@ bool AArch64InstrInfo::areMemAccessesTriviallyDisjoint(
 bool AArch64InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
                                       unsigned &SrcReg2, int &CmpMask,
                                       int &CmpValue) const {
+  // The first operand can be a frame index where we'd normally expect a
+  // register.
+  assert(MI.getNumOperands() >= 2 && "All AArch64 cmps should have 2 operands");
+  if (!MI.getOperand(1).isReg())
+    return false;
+
   switch (MI.getOpcode()) {
   default:
     break;
diff --git a/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp b/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
index 4e65c0a..22c11c7 100644
--- a/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
@@ -167,6 +167,9 @@ AArch64RedundantCopyElimination::knownRegValInBlock(
     // CMP is an alias for SUBS with a dead destination register.
     case AArch64::SUBSWri:
     case AArch64::SUBSXri: {
+      // Sometimes the first operand is a FrameIndex. Bail if tht happens.
+      if (!PredI.getOperand(1).isReg())
+        return None;
       MCPhysReg SrcReg = PredI.getOperand(1).getReg();
 
       // Must not be a symbolic immediate.
diff --git a/llvm/test/CodeGen/AArch64/cmp-frameindex.ll b/llvm/test/CodeGen/AArch64/cmp-frameindex.ll
new file mode 100644
index 0000000..2d01b76
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/cmp-frameindex.ll
@@ -0,0 +1,19 @@
+; RUN: llc -mtriple=aarch64 %s -o - | FileCheck %s
+
+; CHECK: test_frameindex_cmp:
+; CHECK: cmn sp, #{{[0-9]+}}
+define void @test_frameindex_cmp() {
+  %stack = alloca i8
+  %stack.int = ptrtoint i8* %stack to i64
+  %cmp = icmp ne i64 %stack.int, 0
+  br i1 %cmp, label %bb1, label %bb2
+
+bb1:
+  call void @bar()
+  ret void
+
+bb2:
+  ret void
+}
+
+declare void @bar()
-- 
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