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2024-04-03[RISCV][GISEL] Run update_mir_test_checks on llvm/test/CodeGen/RISCV/GlobalIS...Michael Maitland1-44/+44
2024-04-03[SLP]Fix PR87477: fix alternate node cast cost/codegen.Alexey Bataev2-25/+74
2024-04-03[SamplePGO] Support -salvage-stale-profile without probes too (#86116)Krzysztof Pszeniczny3-4/+256
2024-04-03[VectorCombine][X86] Add some tests showing failure to fold shuffle(cast(x),c...Simon Pilgrim1-0/+189
2024-04-03[AMDGPU][MC] Enables sgpr or imm src1 for float VOP3 DPP, but excludi… (#87...Joe Nash19-19/+2055
2024-04-03[NFC] Automatically generate indirect-branch-tracking-eh2.llAmaury Séchet1-48/+172
2024-04-03[SelectionDAG] Dump convergencectrl_glue DAG node (#87487)Jay Foad1-0/+1
2024-04-03[CodeGen] Fix test after #86049Weining Lu1-0/+1
2024-04-03[DAG] visitADDLikeCommutative - convert (add x, shl(0 - y, n)) fold to SDPatt...Simon Pilgrim1-6/+4
2024-04-03[X86] getEffectiveX86CodeModel - take a Triple argument instead of just a Is6...Simon Pilgrim1-3/+4
2024-04-03[DAG] SimplifyDemandedVectorElts - add ISD::AVGCEILS/AVGCEILU/AVGFLOORS/AVGFL...aniplcc3-7/+60
2024-04-03[SLP][NFC]Simplify common analysis of instructions in BoUpSLP::collectValuesT...Alexey Bataev1-107/+78
2024-04-03[VPlan] Factor out logic to check if recipe is dead (NFCI).Florian Hahn1-16/+22
2024-04-03[X86] Add vector truncation tests for nsw/nuw flagsSimon Pilgrim1-0/+2213
2024-04-03[LV] Precommit tests with any-of reductions and epilogue vectorization.Florian Hahn1-0/+222
2024-04-03[VP][DAGCombine] Use `simplifySelect` when combining vp.select. (#87342)AinsleySnow2-0/+60
2024-04-03[X86] Haswell/Broadwell/Skylake DPPS folded instructions use an extra port06 ...Simon Pilgrim12-46/+54
2024-04-03[Object][COFF][NFC] Introduce getMachineArchType helper. (#87370)Jacek Caban3-37/+38
2024-04-03Print more descriptive error message when trying to link a global with append...Gleb Popov2-2/+2
2024-04-03[SLP] Use isValidElementType instead of (#87469)Han-Kuan Chen1-1/+1
2024-04-03[AMDGPU] Remove useless aliases for FLAT instructions. NFC. (#87462)Jay Foad1-2/+2
2024-04-03[PPC] [NFC] add testcase for more store forwardingChen Zheng1-0/+17
2024-04-03[VPlan] Remove VPTransformState::addMetadata with ArrayRef arg (NFCI).Florian Hahn2-18/+5
2024-04-03[CodeGen][ShrinkWrap] Clarify StackAddressUsedBlockInfo meaning (#80679)Elizaveta Noskova1-3/+8
2024-04-03[AArch64][GlobalISel] Basic add_sat and sub_sat vector handling. (#80650)David Green8-427/+775
2024-04-03[ExpandLargeFpConvert] Scalarize vector types. (#86954)Bevin Hansson5-8/+521
2024-04-03[InstCombine] Simplify select if it combinated and/or/xor (#73362)hanbeom2-0/+900
2024-04-02[nfc]Remove the check for compressed strings in llvm/test/.../vtable_profile....Mingming Liu1-4/+1
2024-04-02[dsymutil] Support generating dSYMs for firmware environments (#87432)Jonas Devlieghere4-1/+14
2024-04-03[MIPS] Fix the opcode of max.fmt and mina.fmt (#85609)Cinhi Young7-28/+28
2024-04-02[RISCV] Slightly simplify RVVArgDispatcher::constructArgInfos. NFC (#87308)Craig Topper1-4/+2
2024-04-03Reapply "[CodeGen] Fix register pressure computation in MachinePipeli… (#87...Ryotaro KASUGA3-166/+182
2024-04-03Revert "[PAC][llvm-readobj][AArch64][ELF] Support `GNU_PROPERTY_AARCH64_FEATU...Daniil Kovalev4-303/+157
2024-04-02AMDGPU: Use PseudoInstr instead of Pseudo Mnemonic for SIMCInstr, NFC (#87420)Changpeng Fang1-2/+2
2024-04-03[PAC][llvm-readobj][AArch64][ELF] Support `GNU_PROPERTY_AARCH64_FEATURE_PAUTH...Daniil Kovalev4-157/+303
2024-04-02[LV] Add test depending on target to RISCV subdirectory.Florian Hahn1-0/+0
2024-04-02[VPlan] Make sure OR VPInstructions are treated as disjoint ops.Florian Hahn3-4/+155
2024-04-02[RISCV][NFC] Delete some unused pseudo multiclasses (#87401)Michael Maitland1-26/+0
2024-04-02MachineScheduler: Simplify usage of TargetInstrInfoMatt Arsenault1-12/+4
2024-04-02AMDGPU: Update the description of cache policy for buffer intrinsics, NFC (#8...Changpeng Fang1-285/+233
2024-04-02[CallSiteInfo][NFC] CallSiteInfo -> CallSiteInfo.ArgRegPairs (#86842)Prabhuk10-22/+24
2024-04-02[RISCV] Lower (vector_interleave X, undef) to (vzext_vl X). (#87283)Craig Topper2-14/+16
2024-04-02[RISCV] Add test for miscompile of vector.interleave when odd vector is liter...Craig Topper1-0/+25
2024-04-02[SLP]Fix PR87384: check for fixed vector type before using.Alexey Bataev2-1/+38
2024-04-02[WebAssembly] Allocate MCSymbolWasm data on MCContext (#85866)Tim Neumann9-74/+86
2024-04-02[FPEnv][CostModel] Correct strictfp test.Kevin P. Neal2-2/+2
2024-04-02[X86] canonicalizeShuffleWithOp - don't fold VPERMI(BINOP(X,Y)) -> BINOP(VPER...Simon Pilgrim4-4860/+4473
2024-04-02[SLP]Fix PR80027: handle case when ext is not reduced but its operand is.Alexey Bataev2-0/+55
2024-04-02[RISCV][GISEL] Legalize G_BITCAST for scalable vectors (#85970)Michael Maitland2-0/+362
2024-04-02[ADT] Add signed and unsigned mulh to APInt (#84719)Atousa Duprat5-21/+82
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