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2024-03-20[TTI][TLI][AArch64] Support scalable immediates with isLegalAddImmediate (#84...Graham Hunter2-0/+107
2024-03-20[AArch64] Support scalable offsets with isLegalAddressingMode (#83255)Graham Hunter1-1/+49
2024-03-11[AMDGPU] Use a consistent DwarfEH register flavour (#84513)Emma Pilkington1-0/+2
2024-03-11[llvm][arm] add T1 and T2 assembly options for vlldm and vlstmSivan Shani1-0/+2
2024-03-08[AArch64] Ensure Neoverse-N2 scheduling model includes all SVE pseudos.David Green1-0/+4
2024-03-08[AArch64] Ensure Neoverse V1 scheduling model includes all SVE pseudos. (#84187)David Green1-0/+4
2024-03-06[Unittests] Fix RISCV unit tests buildKrzysztof Parzyszek1-0/+1
2024-03-06[Codegen] Make Width in getMemOperandsWithOffsetWidth a LocationSize. (#83875)David Green1-1/+1
2024-03-06[RISCV] Move RISCVVType namespace to TargetParser (#83222)Wang Pengcheng2-35/+0
2024-02-29Revert "[llvm][arm] add T1 and T2 assembly options for vlldm and vlstm (#83116)"Tomas Matheson1-2/+0
2024-02-28[llvm][arm] add T1 and T2 assembly options for vlldm and vlstm (#83116)SivanShani-Arm1-0/+2
2024-02-26[AMDGPU] Refactor unit test. NFC (#82976)Diana Picus1-13/+22
2024-02-13[SPIRV] Add to LINK_COMPONENTS to fix BUILD_SHARED_LIBS checkJessica Clarke1-0/+1
2024-02-08[RISCV][test] Add test coverage for RISCVInstrInfo::isCopyInstrImplAlex Bradbury1-0/+63
2024-02-02[SPIR-V] add convergence region analysis (#78456)Nathan Gauër2-0/+1116
2024-02-01[AArch64] Replace LLVM IR function attributes for PSTATE.ZA. (#79166)Sander de Smalen1-41/+78
2024-01-20[AArch64][SME2] Preserve ZT0 state around function calls (#78321)Kerry McLaughlin1-0/+36
2024-01-19[AArch64] NFC: Simplify discombobulating 'requiresSMChange' interface (#78703)Sander de Smalen1-47/+12
2024-01-17Revert "[RISCV] Implement RISCVInsrInfo::getConstValDefinedInReg"Alex Bradbury1-46/+0
2024-01-16[AArch64][SME2] Add ZT0 attributes to SMEAttrs (#77607)Kerry McLaughlin1-0/+91
2024-01-16[RISCV] Implement RISCVInsrInfo::getConstValDefinedInReg (#77610)Alex Bradbury1-0/+46
2024-01-02[RISCV][test] Add tests for RISCVInstrInfo::describeLoadedValue (#76041)Alex Bradbury1-0/+78
2023-12-18[RISCV][test] Fix lifetime bug with Module in testAlex Bradbury1-3/+4
2023-12-05[RISCV] Support FrameIndex operands in getMemOperandsWithOffsetWidth / getMem...Alex Bradbury1-2/+7
2023-11-29[RISCV] Pre-commit test for FrameIndex handling in getMemOperandsWithOffsetWidthAlex Bradbury1-0/+13
2023-11-29[RISCV] Implement RISCVInstrInfo::getMemOperandsWithOffsetWidth (#73681)Alex Bradbury1-0/+63
2023-11-16[RISCV] Fix memory leak in RISCVInstrInfoTest.cpp unittestCraig Topper1-4/+6
2023-11-16[RISCV] Implement RISCVInstrInfo::isAddImmediate (#72356)Alex Bradbury2-1/+101
2023-11-16[LoongArch] Set isBarrier to true for instruction 'b' (#72339)ZhaoQi1-6/+2
2023-11-15[LoongArch][NFC] Pre-commit MCInstrAnalysis tests for instruction 'b' (#71903)ZhaoQi1-0/+18
2023-11-10[LoongArch][MC] Refine MCInstrAnalysis based on registers used (#71276)ZhaoQi2-0/+108
2023-11-01[LLVM-C] Fix linking failure introduced by 3351097.Yingwei Zheng1-1/+1
2023-10-31[LLVM-C] Add LLVMCreateTargetMachineWithABI (#68406)Sebastian Poeplau2-0/+82
2023-10-20[RISCV] Add getSameRatioLMUL (#69570)Wang Pengcheng2-0/+35
2023-10-11[LoongArch] Improve codegen for atomic ops (#67391)hev1-1/+1
2023-09-21[VE] Add Core to CMakeLists.txt for VE unittestAmy Kwan1-0/+1
2023-09-20[VE] Add TargetParser to CMakeLists.txt for VE unittestAlex Bradbury1-0/+1
2023-09-20[VE] Add unittest for intrinsics (#66730)Kazushi Marukawa2-0/+335
2023-09-14[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#6...Arthur Eubanks11-16/+16
2023-08-30[AArch64][SME] NFC: Rename hasNewZAInterface to hasNewZABody.Sander de Smalen1-3/+3
2023-07-27[AArch64] Fix build on Windows after 57329ca9463Nico Weber1-3/+3
2023-07-24[AArch64] Ignore instructions not supported by CPU in AArch64SVESchedPseudoTestSander de Smalen1-0/+24
2023-07-04[AArch64] Update SVE scheduling of some CPUsHarvin Iriawan2-0/+91
2023-05-17[RISCV][MC] Refine MCInstrAnalysis based on registers usedJob Noorman2-0/+192
2023-05-03Split out `CodeGenTypes` from `CodeGen` for LLT/MVTNAKAMURA Takumi6-0/+6
2023-04-23[CMake] Target/DirectX: Update depsNAKAMURA Takumi1-0/+1
2023-04-23[CMake] Reorder deps and reformatNAKAMURA Takumi1-1/+1
2023-04-21Recommit "[AArch64] Fix incorrect `isLegalAddressingMode`"Momchil Velikov2-0/+183
2023-04-20Revert "[AArch64] Fix incorrect `isLegalAddressingMode`"Momchil Velikov2-175/+0
2023-04-20[AArch64] Fix incorrect `isLegalAddressingMode`Momchil Velikov2-0/+175
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