| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-04-03 | [GlobalISel] Fix the infinite loop issue in `commute_int_constant_to_rhs` | darkbuck | 1 | -0/+28 |
| 2024-04-04 | [RISCV][TTI] Scale the cost of intrinsic stepvector with LMUL (#87301) | Shih-Po Hung | 1 | -89/+54 |
| 2024-04-03 | [RISCV][GISEL] Instruction selection for G_ZEXT, G_SEXT, and G_ANYEXT with sc... | Michael Maitland | 3 | -0/+2702 |
| 2024-04-03 | [RISCV][GISEL] Regbankselect for G_ZEXT, G_SEXT, and G_ANYEXT with scalable v... | Michael Maitland | 3 | -0/+2460 |
| 2024-04-03 | [RISCV][GISEL] Instruction selection for G_ICMP | Michael Maitland | 1 | -0/+534 |
| 2024-04-03 | [RISCV][GISEL] Regbank select for scalable vector G_ICMP | Michael Maitland | 1 | -0/+675 |
| 2024-04-03 | [RISCV][GISEL] Legalize G_ZEXT, G_SEXT, and G_ANYEXT, G_SPLAT_VECTOR, and G_I... | Michael Maitland | 9 | -8/+7222 |
| 2024-04-03 | [VectorCombine][X86] shuffle-of-casts.ll - adjust zext nneg tests to improve ... | Simon Pilgrim | 1 | -16/+16 |
| 2024-04-03 | [SLP]Improve minbitwidth analysis for operands of IToFP and ICmp instructions. | Alexey Bataev | 2 | -6/+8 |
| 2024-04-03 | Revert "[SLP]Improve minbitwidth analysis for operands of IToFP and ICmp inst... | Alexey Bataev | 2 | -8/+6 |
| 2024-04-03 | [SLP]Improve minbitwidth analysis for operands of IToFP and ICmp instructions. | Alexey Bataev | 2 | -6/+8 |
| 2024-04-03 | [AMDGPU] Add a missing COV6 case to getAMDHSACodeObjectVersion() (#87492) | Emma Pilkington | 1 | -0/+7 |
| 2024-04-03 | [AMDGPU][MC] Allow VOP3C dpp src1 to be imm or SGPR (#87418) | Joe Nash | 11 | -25/+3216 |
| 2024-04-03 | [AArch64] Add a test for non-temporal masked loads / stores. NFC | David Green | 1 | -0/+75 |
| 2024-04-03 | [VectorCombine][X86] Add additional tests for #87510 | Simon Pilgrim | 1 | -0/+42 |
| 2024-04-03 | [SLP]Add support for commutative intrinsics. | Alexey Bataev | 5 | -19/+18 |
| 2024-04-03 | [PseudoProbe] Mix block and call probe ID in lexical order (#75092) | Lei Wang | 9 | -54/+56 |
| 2024-04-03 | Always check the function attribute to determine checksum mismatch for availa... | Lei Wang | 1 | -3/+6 |
| 2024-04-03 | [SLP]Fix PR87133: crash because of different altopcodes for cmps after reorde... | Alexey Bataev | 2 | -22/+80 |
| 2024-04-03 | [RISCV][GISEL] Run update_mir_test_checks on llvm/test/CodeGen/RISCV/GlobalIS... | Michael Maitland | 1 | -44/+44 |
| 2024-04-03 | [SLP]Fix PR87477: fix alternate node cast cost/codegen. | Alexey Bataev | 1 | -0/+34 |
| 2024-04-03 | [SamplePGO] Support -salvage-stale-profile without probes too (#86116) | Krzysztof Pszeniczny | 2 | -0/+252 |
| 2024-04-03 | [VectorCombine][X86] Add some tests showing failure to fold shuffle(cast(x),c... | Simon Pilgrim | 1 | -0/+189 |
| 2024-04-03 | [AMDGPU][MC] Enables sgpr or imm src1 for float VOP3 DPP, but excludi… (#87... | Joe Nash | 15 | -10/+2022 |
| 2024-04-03 | [NFC] Automatically generate indirect-branch-tracking-eh2.ll | Amaury Séchet | 1 | -48/+172 |
| 2024-04-03 | [CodeGen] Fix test after #86049 | Weining Lu | 1 | -0/+1 |
| 2024-04-03 | [DAG] SimplifyDemandedVectorElts - add ISD::AVGCEILS/AVGCEILU/AVGFLOORS/AVGFL... | aniplcc | 2 | -7/+56 |
| 2024-04-03 | [X86] Add vector truncation tests for nsw/nuw flags | Simon Pilgrim | 1 | -0/+2213 |
| 2024-04-03 | [LV] Precommit tests with any-of reductions and epilogue vectorization. | Florian Hahn | 1 | -0/+222 |
| 2024-04-03 | [VP][DAGCombine] Use `simplifySelect` when combining vp.select. (#87342) | AinsleySnow | 1 | -0/+53 |
| 2024-04-03 | [X86] Haswell/Broadwell/Skylake DPPS folded instructions use an extra port06 ... | Simon Pilgrim | 8 | -38/+38 |
| 2024-04-03 | Print more descriptive error message when trying to link a global with append... | Gleb Popov | 1 | -1/+1 |
| 2024-04-03 | [PPC] [NFC] add testcase for more store forwarding | Chen Zheng | 1 | -0/+17 |
| 2024-04-03 | [AArch64][GlobalISel] Basic add_sat and sub_sat vector handling. (#80650) | David Green | 7 | -422/+767 |
| 2024-04-03 | [ExpandLargeFpConvert] Scalarize vector types. (#86954) | Bevin Hansson | 4 | -0/+480 |
| 2024-04-03 | [InstCombine] Simplify select if it combinated and/or/xor (#73362) | hanbeom | 1 | -0/+794 |
| 2024-04-02 | [nfc]Remove the check for compressed strings in llvm/test/.../vtable_profile.... | Mingming Liu | 1 | -4/+1 |
| 2024-04-02 | [dsymutil] Support generating dSYMs for firmware environments (#87432) | Jonas Devlieghere | 3 | -0/+11 |
| 2024-04-03 | [MIPS] Fix the opcode of max.fmt and mina.fmt (#85609) | Cinhi Young | 6 | -24/+24 |
| 2024-04-03 | Reapply "[CodeGen] Fix register pressure computation in MachinePipeli… (#87... | Ryotaro KASUGA | 2 | -165/+181 |
| 2024-04-03 | Revert "[PAC][llvm-readobj][AArch64][ELF] Support `GNU_PROPERTY_AARCH64_FEATU... | Daniil Kovalev | 2 | -211/+96 |
| 2024-04-03 | [PAC][llvm-readobj][AArch64][ELF] Support `GNU_PROPERTY_AARCH64_FEATURE_PAUTH... | Daniil Kovalev | 2 | -96/+211 |
| 2024-04-02 | [LV] Add test depending on target to RISCV subdirectory. | Florian Hahn | 1 | -0/+0 |
| 2024-04-02 | [VPlan] Make sure OR VPInstructions are treated as disjoint ops. | Florian Hahn | 1 | -0/+132 |
| 2024-04-02 | [RISCV] Lower (vector_interleave X, undef) to (vzext_vl X). (#87283) | Craig Topper | 1 | -13/+6 |
| 2024-04-02 | [RISCV] Add test for miscompile of vector.interleave when odd vector is liter... | Craig Topper | 1 | -0/+25 |
| 2024-04-02 | [SLP]Fix PR87384: check for fixed vector type before using. | Alexey Bataev | 1 | -0/+35 |
| 2024-04-02 | [WebAssembly] Allocate MCSymbolWasm data on MCContext (#85866) | Tim Neumann | 1 | -0/+25 |
| 2024-04-02 | [FPEnv][CostModel] Correct strictfp test. | Kevin P. Neal | 2 | -2/+2 |
| 2024-04-02 | [X86] canonicalizeShuffleWithOp - don't fold VPERMI(BINOP(X,Y)) -> BINOP(VPER... | Simon Pilgrim | 3 | -4855/+4464 |
