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2024-01-24[𝘀𝗽𝗿] changes to main this commit is based onusers/minglotus-6/sprmain.thinltomingmingl25-34/+535
2024-01-23[RISCV] Add regalloc hints for Zcb instructions. (#78949)Craig Topper1-0/+86
2024-01-23[DebugInfo][RemoveDIs] Disable a run-line while investigating a problemJeremy Morse1-1/+2
2024-01-23[JITLink][AArch32] Implement Armv5 ldr-pc stubs and use them for all pre-v7 t...Stefan Gränitz9-199/+321
2024-01-23[RemoveDIs][DebugInfo] Enable creation of DPVAssigns, update outstanding AT t...Stephen Tozer19-0/+41
2024-01-23[AMDGPU] Enable architected SGPRs for GFX12 (#79160)Jay Foad3-85/+175
2024-01-23[DAG] visitSCALAR_TO_VECTOR - don't fold scalar_to_vector(bin(extract(x),extr...Simon Pilgrim1-51/+31
2024-01-23[DebugInfo][RemoveDIs] Use splice in Outliner rather than moveBefore (#79124)Jeremy Morse1-0/+1
2024-01-23[AMDGPU] Properly check op_sel in GCNDPPCombine (#79122)Mirko BrkuĹĄanin1-4/+80
2024-01-23[RemoveDIs][DebugInfo] Handle DPVAssign in most transforms (#78986)Stephen Tozer31-2/+51
2024-01-23[LAA] Add test for #79137 (NFC)Nikita Popov1-0/+94
2024-01-23[X86] Add test case for Issue #78897Simon Pilgrim1-0/+313
2024-01-23[DebugInfo][RemoveDIs] Handle non-instr debug-info in GlobalISel (#75228)Jeremy Morse6-8/+19
2024-01-23[llvm-reduce][DebugInfo] Support reducing non-instruction debug-info (#78995)Jeremy Morse1-0/+51
2024-01-23[RemoveDIs][DebugInfo] Handle DPVAssigns in Assignment Tracking excluding low...Stephen Tozer36-0/+180
2024-01-23[test] Update stack_guard_remat.ll (#79139)Danial Klimkin1-1/+1
2024-01-23ValueTracking: Recognize fcmp ole/ugt with inf as a class test (#79095)Matt Arsenault2-18/+15
2024-01-23[AArch64] Add vec3 tests with add between load and store.Florian Hahn1-0/+106
2024-01-23[MC][X86] Merge lane/element broadcast comment printers. (#79020)Simon Pilgrim111-3873/+3873
2024-01-23[AMDGPU] Handle V_PERMLANE64_B32 in fixVcmpxPermlaneHazards (#79125)Pierre van Houtryve1-0/+23
2024-01-23[AMDGPU] Update llvm-objdump lit tests for COV5 (#79039)Saiyedul Islam7-0/+20
2024-01-23[PhaseOrder] Add test where indvars dropping NSW prevents vectorization.Florian Hahn1-0/+68
2024-01-23[X86] canonicalizeShuffleWithOp - recognise constant vectors with getTargetCo...Simon Pilgrim12-2313/+2259
2024-01-23Reapply [hwasan] Update dbg.assign intrinsics in HWAsan pass #78606OCHyams4-1/+202
2024-01-23[SCEVExp] Add additional tests for hoisting IVs with NSW flags.Florian Hahn1-0/+88
2024-01-23[InstCombine] Remove one-use check if other logic operand is constant (#77973)AtariDreams1-0/+30
2024-01-23[RemoveDIs][NFC] Disable RemoveDIs tests that are not yet enabledStephen Tozer3-6/+0
2024-01-23test/llvm-cov: Regenerate mcdc-maxbs.o w/o zlib (#78963)NAKAMURA Takumi2-0/+1
2024-01-23[dsymutil] Add --linker parallel to more tests. (#78581)Alexey Lapshin9-0/+40
2024-01-23[AMDGPU][True16] Support source DPP operands. (#79025)Ivan Kosarev4-87/+138
2024-01-23[RemoveDIs][DebugInfo] Update SROA to handle DPVAssigns (#78475)Stephen Tozer21-0/+33
2024-01-23[X86][CodeGen] Add entries for NDD SHLD/SHRD to the commuteInstructionImplShengchen Kan2-24/+25
2024-01-23[Coverage] getMaxBitmapSize: Scan `max(BitmapIdx)` instead of the last `Decis...NAKAMURA Takumi4-0/+68
2024-01-23Reland "[llvm][AArch64] Copy all operands when expanding BLR_BTI bundle (#782...David Spickett2-23/+28
2024-01-23[CodeGen][LoongArch] Set FP_TO_SINT/FP_TO_UINT to legal for vector types (#79...yjijd4-0/+170
2024-01-23[CodeGen][LoongArch] Set SINT_TO_FP/UINT_TO_FP to legal for vector types (#78...yjijd4-0/+170
2024-01-22[RISCV] Fix stack size computation when M extension disabled (#78602)Simeon K1-0/+62
2024-01-23[LoongArch] Add definitions and feature 'frecipe' for FP approximation intrin...Ami-zhang6-0/+156
2024-01-22Arm64EC entry/exit thunks, consolidated. (#79067)Eli Friedman8-9/+1040
2024-01-23ValueTracking: Handle fcmp true/false in fcmpToClassTestMatt Arsenault1-16/+16
2024-01-23ValueTracking: Add tests for fcmpToClassTest for fcmp ole/ugt infMatt Arsenault1-0/+104
2024-01-23ValueTracking: Add tests fcmpToClassTest for fcmp true/falseMatt Arsenault1-0/+286
2024-01-22nfc add test cases for PowerPC vector instructions cost analysisChen Zheng1-0/+235
2024-01-23[RISCV][CostModel] Make VMV_S_X and VMV_X_S cost independent of LMUL (#78739)Shih-Po Hung2-8/+8
2024-01-23[JITLink][AArch32] Implement R_ARM_PREL31 and process .ARM.exidx sections (#7...Stefan Gränitz1-4/+16
2024-01-23[X86] Support encoding/decoding and lowering for APX variant SHL/SHR/SAR/ROL/...Shengchen Kan35-0/+10368
2024-01-23[JITLink][AArch32] Multi-stub support for armv7/thumbv7 (#78371)Stefan Gränitz2-0/+103
2024-01-23[RISCV] Merge ADDI with X0 into base offset (#78940)Jim Lin1-20/+8
2024-01-23[AMDGPU] SILowerSGPRSpills: do not update MRI reserve registers (#77888)Carl Ritson1-1/+1
2024-01-23[LoongArch] Permit auto-vectorization using LSX/LASX with `auto-vec` feature ...wanglei2-0/+69
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