aboutsummaryrefslogtreecommitdiff
path: root/llvm/test/tools/llvm-mca/AArch64
AgeCommit message (Expand)AuthorFilesLines
2024-04-02[AArch64] Update Neoverse V2 FSQRT execution units in schedule model. (#86803)Rin Dobrescu1-7/+7
2024-03-25[AArch64] Correct Neoverse V1 SVE 16-bit sdot/udot schedule pipelines. (#86142)David Green1-9/+9
2024-03-05[LLVM][AArch64][CodeGen] Mark FFR as a reserved register. (#83437)Paul Walker5-20/+20
2024-02-26[CodeGenSchedule] Don't allow invalid ReadAdvances to be formed (#82685)Visoiu Mistrih Francis1-6/+6
2024-02-22[AArch64] Fix sched model for TSV110 core. (#82343)Yury Gribov1-0/+83
2024-02-14[AArch64] Initial Ampere1B scheduling model (#81341)Philipp Tomsich5-0/+7415
2024-02-01[AArch64] Alter latency of FCSEL under Cortex-A510 (#80178)David Green1-2/+2
2023-10-12[AArch64] Fix schedmodel pre/post-index loads and stores for TSV110zhongyunde 004434071-1128/+1123
2023-10-12[test] precommit sched model for tsv110, NFCzhongyunde 004434071-0/+3959
2023-10-12[AArch64] Fix postinc operands for Cortex-A57 schedulingDavid Green1-1785/+1784
2023-10-11[AArch64] Fix postinc operands for Neoverse-N2 schedulingDavid Green1-1925/+1914
2023-10-11[AArch64] Fix postinc operands for Neoverse-N1 schedulingDavid Green1-2045/+2034
2023-10-11[AArch64] Fix postinc operands for Neoverse-V1 schedulingDavid Green1-2083/+2067
2023-10-10[AArch64] Fix postinc operands for Cortex-A55 schedulingDavid Green1-1156/+1156
2023-10-10[AArch64] Fix postinc operands for Cortex-A53 schedulingDavid Green1-1156/+1156
2023-10-10[AArch64] Fix postinc operands for Cortex-A510 schedulingDavid Green1-1019/+1019
2023-10-07[AArch64] Tests for postinc scheduling write operands. NFCDavid Green7-0/+37081
2023-09-07[AArch64] Fix schedmodel zero latency moves for Neoverse V2Ricardo Jesus2-11/+86
2023-09-04[AArch64] Fix schedmodel pre/post-index loads and stores for Neoverse V2Sjoerd Meijer1-0/+3979
2023-07-17[AArch64] Add scheduling model for Neoverse V1Evandro Menezes4-37/+14663
2023-07-01[AArch64] Add scheduling model for Neoverse N1Evandro Menezes2-0/+6955
2023-06-27[test] Replace aarch64-*-eabi with aarch64Fangrui Song1-1/+1
2023-06-20[AArch64] Add Cortex-A510 specific schedulingHarvin Iriawan3-0/+17202
2023-06-14[AArch64] Neoverse V2 scheduling modelRicardo Jesus4-0/+19730
2023-05-17[NFC][Py Reformat] Reformat lit.local.cfg python files in llvmTobias Hieta1-1/+1
2023-03-10[AArch64] Fix N2 SchedModel for arithmetic and logic ops with cheap LSLRicardo Jesus1-153/+153
2023-02-22[AArch64] Fix N2 SchedModel element-to-element INS latenciesSjoerd Meijer1-1/+25
2023-01-25[SVE][InstrFormats] Explcitly set hasSideEffects for all SVE instructions.Paul Walker2-848/+848
2022-12-28[AArch64][MachineScheduler] Set no side effect for movprfxzhongyunde2-2/+2
2022-12-14[AArch64][SVE][ISel] Combine dup of load to replicating loadPeter Waller2-64/+64
2022-10-14[AArch64]Change printVectorList to print SVE vector rangeCaroline Concatto2-320/+320
2022-08-25[AArch64][SVE] Extend LD1RQ ISel patterns to cover missing addressing modesMatt Devereau2-8/+8
2022-08-25[AArch64] Fix sched model for tsv110zhongyunde1-492/+522
2022-08-18[NFC][AArch64] precommit sched model for tsv110zhongyunde1-0/+3705
2022-08-09[AArch64] Fix and add A64FX scheduling resource/latency infoYuta Mukai3-0/+14442
2022-08-05[AArch64] Tone down the number of repeated fmov N2 scheduling tests. NFCDavid Green1-1525/+1
2022-07-12[MCA] Support multiple comma-separated -mattr featuresCullen Rhodes1-6/+1
2022-07-08[AArch64] Use Neoverse N2 sched model as default for:Cullen Rhodes4-0/+160
2022-07-08[AArch64] Initial sched model for Neoverse N2Cullen Rhodes4-0/+19078
2022-02-28Partially revert "[SchedModels][CortexA55] Add ASIMD integer instructions"David Green1-109/+109
2022-02-17[SchedModels][CortexA55] Add ASIMD integer instructionsPavel Kosov1-475/+475
2022-01-11[MCA] Switching from conservatively guessing which instructions arePatrick Holland1-22/+22
2022-01-10[SchedModels][CortexA55] Fix scheduling of FP loadsPavel Kosov2-195/+195
2021-09-29[AArch64] Model Cortex-A55 Q register NEON instructionsDavid Green1-929/+929
2021-08-26[AArch64] Remove unpredictable from narrowing instructions.David Green1-15/+15
2021-08-26[AArch64] Add a Cortex-A55 NEON scheduler test case.David Green1-0/+3211
2021-08-23[AArch64] Correct store ReadAdrBase operandDavid Green1-123/+123
2021-08-23[AArch64] Add Scheduling tests for Load/Store ReadAdv operands.David Green2-0/+1482
2021-07-29[MCA] Use LSU for the in-order pipelineAndrew Savonichev2-29/+154
2021-07-16[AArch64] Update Cortex-A55 SchedModel to improve LDP schedulingNicholas Guy1-79/+79
generated by cgit v1.1 at 2024-09-07 12:25:36 +0000