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AgeCommit message (Expand)AuthorFilesLines
2024-02-23Remove duplicated REQUIRES: assertsBenjamin Kramer1-1/+0
2024-02-22LoopVectorize/test: guard pr72969 with asserts (#82653)Ramkumar Ramachandra1-0/+1
2024-02-22LoopVectorize: Mark crash test as requiring assertionsBenjamin Kramer1-0/+1
2024-02-22LoopVectorize: add test for crash in #72969 (#74111)Ramkumar Ramachandra1-0/+25
2024-02-15Adding support of AMDLIBM vector library (#78560)Rohit Aggarwal2-0/+1201
2024-02-05[LV] Remove loop trip count threshold for deciding whether to interleave a lo...Nilanjana Basu10-1135/+1785
2024-01-31[VPlan] Preserve original induction order when creating scalar steps.Florian Hahn2-25/+25
2024-01-25[llvm][LV] Move new test into X86 subfolderDavid Spickett1-0/+86
2024-01-24[InstCombine] Canonicalize constant GEPs to i8 source element type (#68882)Nikita Popov8-493/+482
2024-01-09[LV] Create block in mask up-front if needed. (#76635)Florian Hahn4-63/+63
2024-01-07[VPlan] Manage InBounds via VPRecipeWithIRFlags for VectorPtrRecipe.Florian Hahn1-3/+4
2024-01-07[LV] Add test showing overly aggressive dropping of inbounds.Florian Hahn1-0/+50
2024-01-05[InstCombine] Revert the `signed icmp -> unsigned icmp` canonicalization when...Yingwei Zheng3-57/+53
2024-01-04[LV] Change loops' interleave count computation (#73766)Nilanjana Basu1-3/+3
2024-01-01[VPlan] Model address separately. (#72164)Florian Hahn13-283/+283
2023-12-06[ValueTracking] Add dominating condition support in computeKnownBits() (#73662)Nikita Popov3-27/+27
2023-12-05[VPlan] Add disjoint flag to VPRecipeWithIRFlags. (#74364)Florian Hahn1-1/+1
2023-12-05[LV]Support dropping of nneg flag for zext widencast recipes. (#74112)Alexey Bataev1-0/+78
2023-12-05[Tests] Add disjoint flag to some tests (NFC)Nikita Popov5-19/+19
2023-12-02[InstCombine] Infer disjoint flag on Or instructions. (#72912)Craig Topper4-32/+32
2023-11-27[InstCombine] Set disjoint flag when turning Add into Or. (#72702)Craig Topper6-28/+28
2023-11-17[LV] Pre-committing tests for changing loop interleaving count computation (#...Nilanjana Basu1-17/+237
2023-11-17[LV] Reverse mask up front, not when creating vector pointer. (#72163)Florian Hahn1-8/+8
2023-11-13[CVP] Infer nneg on existing zext (#72052)Yingwei Zheng1-4/+4
2023-11-03[LV] Support recieps without underlying instr in collectPoisonGenRec.Florian Hahn1-0/+83
2023-10-24BlockFrequencyInfoImpl: Avoid big numbers, increase precision for small spreadsMatthias Braun2-11/+14
2023-10-12[LoopVectorize] Regenerate test checks (NFC)Nikita Popov3-226/+226
2023-09-20[InferAlignment] Enable InferAlignment pass by defaultDhruv Chawla2-7/+7
2023-09-11[InstCombine] Generalize foldICmpWithMinMaxYingwei Zheng1-20/+19
2023-08-29[LV] Use IRBuilder to create and optimize middle-block compare.Florian Hahn16-435/+101
2023-08-09[LV] Move interleaved test to X86 directoryAnna Thomas1-0/+96
2023-08-08[LV] Complete load groups and release store groups. Try 2.Anna Thomas2-51/+70
2023-08-01Recommit "[LV] Re-use existing broadcast value for live-ins."Florian Hahn4-156/+120
2023-08-01[InstCombine] Set dead phi inputs to poison in more casesNikita Popov1-10/+5
2023-07-26Revert "[LV] Complete load groups and release store groups in presence of dep...Anna Thomas2-70/+51
2023-07-25[LV] Complete load groups and release store groups in presence of dependencyAnna Thomas2-51/+70
2023-07-25Revert "[LV] Re-use existing broadcast value for live-ins."Martin Storsjö4-120/+156
2023-07-24[LV] Re-use existing broadcast value for live-ins.Florian Hahn4-156/+120
2023-07-17[LV] Precommit test for interleaving miscompileAnna Thomas1-0/+102
2023-07-14Precommit follow-up testcase for interleaved miscompileAnna Thomas1-1/+112
2023-07-07[LV] Skip VFs > # iterations remaining for epilogue vectorization.Florian Hahn3-89/+59
2023-07-07Revert "[LV] Skip VFs < iterations remaining for epilogue vectorization."Florian Hahn3-59/+89
2023-07-07[LV] Skip VFs < iterations remaining for epilogue vectorization.Florian Hahn3-89/+59
2023-07-07[LV] Do not add load to group if it moves across conflicting store.Florian Hahn1-22/+24
2023-07-06[LV] Consider if scalar epilogue is required in getMaximizedVFForTarget.Florian Hahn2-46/+24
2023-07-04[LV] Regenerate check lines to reduced diff.Florian Hahn1-16/+16
2023-07-03[LV] Prepare tests for D154261.Florian Hahn2-21/+94
2023-07-03[LV] Check for vector instruction in main vector loop.Florian Hahn1-1/+1
2023-07-02[LV] Add test case for #63602.Florian Hahn1-0/+113
2023-06-30[LV] Add additional tests with dead vector epilogues.Florian Hahn1-11/+214
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