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path: root/llvm/test/Transforms/LoopVectorize/RISCV
AgeCommit message (Expand)AuthorFilesLines
2024-02-22[RISCV][LV] Add additional small trip count loop coveragePhilip Reames1-2/+366
2024-02-22[RISCV][AArch64] Add vscale_range attribute to tests per architecture minimumsPhilip Reames1-1/+1
2024-02-06[test] Regen a test for naming changesPhilip Reames1-20/+20
2024-01-09[LV] Create block in mask up-front if needed. (#76635)Florian Hahn1-4/+4
2024-01-01[VPlan] Model address separately. (#72164)Florian Hahn4-23/+27
2023-12-08[VPlan] Initial modeling of VF * UF as VPValue. (#74761)Florian Hahn11-92/+94
2023-12-08[VPlan] Compute scalable VF in preheader for induction increment. (#74762)Florian Hahn15-372/+372
2023-10-26[opt] Infer DataLayout from triple if not specifiedAlex Richardson4-69/+251
2023-10-16 [LV] Replace value numbers with patterns in tests (NFC).Florian Hahn1-14/+14
2023-10-05[IR]Add NumSrcElts param to is..Mask static function in ShuffleVectorInst.Alexey Bataev1-27/+4
2023-10-05[AArch64] [LoopVectorize] Use either fixed-width or scalable VF when tail-fol...Rin1-16/+38
2023-10-04Revert "[IR]Add NumSrcElts param to is..Mask static function in ShuffleVector...Arthur Eubanks1-4/+27
2023-10-04Regenerate test checks for tests affected by D141060Alex Richardson1-14/+14
2023-10-04[IR]Add NumSrcElts param to is..Mask static function in ShuffleVectorInst.Alexey Bataev1-27/+4
2023-10-03Revert "[IR]Add NumSrcElts param to is..Mask static function in ShuffleVector...Alexey Bataev1-4/+27
2023-10-03[IR]Add NumSrcElts param to is..Mask static function in ShuffleVectorInst.Alexey Bataev1-27/+4
2023-09-29Revert "[IR]Add NumSrcElts param to is..Mask static function in ShuffleVector...Alexey Bataev1-4/+27
2023-09-29[IR]Add NumSrcElts param to is..Mask static function in ShuffleVectorInst.Alexey Bataev1-27/+4
2023-09-28Revert "[IR]Add NumSrcElts param to is..Mask static function in ShuffleVector...Alexey Bataev1-4/+27
2023-09-28[IR]Add NumSrcElts param to is..Mask static function in ShuffleVectorInst.Alexey Bataev1-27/+4
2023-09-25[RISCV][CostModel] Add getCFInstrCost RISC-V implementation (#65599)Sergey Kachkov3-29/+38
2023-09-18[VPlan] Fold (MUL A, 1) -> A as VPlan2VPlan transform.Florian Hahn1-24/+22
2023-08-29[LV] Use IRBuilder to create and optimize middle-block compare.Florian Hahn5-48/+24
2023-08-08[VPlan] Model wrap flags directly, remove *NUW opcodes (NFC)Florian Hahn1-2/+2
2023-08-08[VPlan] Use printOperands for VPInstruction.Florian Hahn1-2/+2
2023-08-01Recommit "[LV] Re-use existing broadcast value for live-ins."Florian Hahn3-47/+21
2023-07-25Revert "[LV] Re-use existing broadcast value for live-ins."Martin Storsjö3-21/+47
2023-07-24[LV] Re-use existing broadcast value for live-ins.Florian Hahn3-47/+21
2023-07-18[RISCV][CostModel] Model vrgather.vv as being quadradic in LMULPhilip Reames2-61/+41
2023-07-07[RISCV] Update loop vectorizer interleaved access test outputLuke Lau1-23/+12
2023-06-13[VPlan] Replace versioned stride with constant during VPlan opts.Florian Hahn1-28/+24
2023-06-12[LoopVectorize] Convert most tests to opaque pointers (NFC)Nikita Popov1-81/+67
2023-05-23[VPlan] Print IR flags for VPRecipeWithIRFlags.Florian Hahn1-6/+6
2023-05-17[NFC][Py Reformat] Reformat lit.local.cfg python files in llvmTobias Hieta1-2/+2
2023-05-01[LAA] Add command line flag to disable unit stride speculationPhilip Reames1-269/+405
2023-04-27[IR] Change shufflevector undef mask to poisonManuelJBrito1-1/+1
2023-04-13[IR] llvm::createMinMaxOp - create integer min/max intrinsics instead of icmp...Simon Pilgrim1-6/+4
2023-04-12[LV] Optimize trip count SCEV.Craig Topper1-44/+40
2023-04-09[LV] Update tests checking VPlans to use patterns for VPValues.Florian Hahn1-14/+14
2023-04-05[IVDescriptors] Add pointer InductionDescriptors with non-constant strides (t...Philip Reames1-18/+107
2023-04-05[RISCV] Account for LMUL in memory op costsPhilip Reames4-55/+62
2023-04-04[RISCV] Model vlseg/vsseg in interleaved memory opsLuke Lau2-67/+63
2023-03-31Revert "[IVDescriptors] Add pointer InductionDescriptors with non-constant st...David Green1-75/+5
2023-03-30[IVDescriptors] Add pointer InductionDescriptors with non-constant stridesPhilip Reames1-5/+75
2023-03-30[RISCV][LV] Add test coverage for strided access patterns [nfc]Philip Reames1-0/+576
2023-03-28[RISCV] Cost model for general case of single vector permutePhilip Reames1-9/+37
2023-03-24[NFC][LoopVectorize] Change trip counts for some tests to guarantee a scalar ...David Sherwood2-210/+285
2023-03-23[RISCV] Increase default vectorizer LMUL to 2Luke Lau18-1341/+1486
2023-03-22[RISCV][NFC] Make interleaved access test more vectorizableLuke Lau1-28/+34
2023-03-16Mark test added in D145155 as requiring asserts since it uses the "-debug-onl...Douglas Yung1-0/+1
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