| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-04-03 | [RISCV][GISEL] Legalize G_ZEXT, G_SEXT, and G_ANYEXT, G_SPLAT_VECTOR, and G_I... | Michael Maitland | 2 | -8/+18 |
| 2024-04-01 | [GISEL] G_SPLAT_VECTOR can take a splat that is larger than the vector elemen... | Michael Maitland | 1 | -2/+2 |
| 2024-03-23 | [GlobalISel] Introduce G_TRAP, G_DEBUGTRAP, G_UBSANTRAP (#84941) | Evgenii Kudriashov | 1 | -0/+18 |
| 2024-03-21 | Reapply "Move assertion for AdjustsStack from PEI to MachineVerifier (#85698)" | Jonas Paulsson | 1 | -0/+26 |
| 2024-03-20 | Revert "Move assertion for AdjustsStack from PEI to MachineVerifier. (#85698)" | Jonas Paulsson | 1 | -26/+0 |
| 2024-03-20 | Move assertion for AdjustsStack from PEI to MachineVerifier. (#85698) | Jonas Paulsson | 1 | -0/+26 |
| 2024-03-12 | [GISEL] Add G_VSCALE instruction (#84542) | Michael Maitland | 1 | -0/+15 |
| 2024-03-11 | [GISEL] Add G_INSERT_SUBVECTOR and G_EXTRACT_SUBVECTOR (#84538) | Michael Maitland | 2 | -0/+74 |
| 2024-03-09 | [GISel] Enforce G_PTR_ADD RHS type matching index size for addr space (#84352) | Jay Foad | 1 | -1/+5 |
| 2024-03-07 | [AMDGPU,test] Change llc -march= to -mtriple= | Fangrui Song | 4 | -4/+4 |
| 2024-03-07 | [GISEL] Add IRTranslation for shufflevector on scalable vector types (#80378) | Michael Maitland | 1 | -0/+27 |
| 2024-03-07 | Revert "[GISEL] Add IRTranslation for shufflevector on scalable vector types"... | Michael Maitland | 1 | -27/+0 |
| 2024-03-07 | [GISEL] Add IRTranslation for shufflevector on scalable vector types (#80378) | Michael Maitland | 1 | -0/+27 |
| 2024-03-06 | Restore "Implement convergence control in MIR using SelectionDAG (#71785)" | Sameer Sahasrabuddhe | 5 | -0/+130 |
| 2024-03-04 | Revert "Restore "Implement convergence control in MIR using SelectionDAG (#71... | Mitch Phillips | 5 | -130/+0 |
| 2024-03-04 | Restore "Implement convergence control in MIR using SelectionDAG (#71785)" | Sameer Sahasrabuddhe | 5 | -0/+130 |
| 2024-02-21 | Revert "Implement convergence control in MIR using SelectionDAG (#71785)" | Sameer Sahasrabuddhe | 6 | -141/+0 |
| 2024-02-21 | Implement convergence control in MIR using SelectionDAG (#71785) | Sameer Sahasrabuddhe | 6 | -0/+141 |
| 2024-01-30 | [FIX] Require AMDGPU target in test case `llvm/test/MachineVerifier/writelane... | Shilei Tian | 1 | -0/+2 |
| 2024-01-30 | [AMDGPU][AsmParser] Allow `v_writelane_b32` to use SGPR and M0 as source oper... | Shilei Tian | 1 | -0/+16 |
| 2024-01-16 | [AMDGPU,test] Change llc -march= to -mtriple= (#75982) | Fangrui Song | 3 | -3/+3 |
| 2023-12-11 | [GlobalISel] Add G_PREFETCH (#74863) | Jay Foad | 1 | -0/+40 |
| 2023-11-30 | MachineVerifier: Reject extra non-register operands on instructions (#73758) | Matt Arsenault | 1 | -0/+30 |
| 2023-11-07 | [MachineVerifier] Fix COPY check in MachineVerifier for scalable vectors | Michael Maitland | 1 | -2/+41 |
| 2023-11-07 | [CodeGen][MachineVerifier] Use TypeSize instead of unsigned for getRe… (#70... | Michael Maitland | 1 | -0/+23 |
| 2023-10-30 | [GISel] Restrict G_BSWAP to multiples of 16 bits. (#70245) | Craig Topper | 1 | -0/+19 |
| 2023-09-29 | [test] -march -> -mtriple (#67741) | Visoiu Mistrih Francis | 2 | -2/+2 |
| 2023-09-29 | [test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64 | Fangrui Song | 41 | -41/+41 |
| 2023-09-01 | MachineVerifier: Add tests which are incorrectly accepted | Matt Arsenault | 3 | -0/+64 |
| 2023-08-21 | [AArch64] Update generic sched model to A510 | Harvin Iriawan | 1 | -1/+1 |
| 2023-04-18 | [X86] Fix checks for illegal physreg COPY instructions | Jay Foad | 1 | -3/+11 |
| 2023-02-14 | [PowerPC][GISel] add support for fpconstant | Chen Zheng | 1 | -0/+40 |
| 2022-12-07 | [GlobalISel] Add a new G_INVOKE_REGION_START instruction to fix an EH bug. | Amara Emerson | 1 | -0/+22 |
| 2022-11-17 | [GlobalISel] Better verification of G_UNMERGE_VALUES | Jay Foad | 1 | -0/+33 |
| 2022-11-15 | [GlobalISel] Remove semantic operand of G_IS_FPCLASS | Serge Pavlov | 1 | -10/+7 |
| 2022-09-22 | [GlobalISel] Enforce G_ASSERT_ALIGN to have a valid alignment > 0. | Amara Emerson | 1 | -0/+17 |
| 2022-09-22 | MachineVerifier: Verify REG_SEQUENCE | Matt Arsenault | 1 | -0/+59 |
| 2022-09-05 | [MachineVerifier] Fix crash on early clobbered subreg operands. | Daniil Fukalov | 1 | -0/+31 |
| 2022-08-19 | [MachineVerifier] add checks for INLINEASM_BR | Nick Desaulniers | 1 | -0/+178 |
| 2022-05-27 | [GlobalISel] Add G_IS_FPCLASS | Serge Pavlov | 1 | -0/+40 |
| 2022-04-22 | GlobalISel: Relax handling of G_ASSERT_* with source register classes | Matt Arsenault | 2 | -16/+18 |
| 2022-04-11 | GlobalISel: Verify atomic load/store ordering restriction | Matt Arsenault | 2 | -0/+12 |
| 2022-04-05 | MachineVerifier: Diagnose undef set on full register defs | Matt Arsenault | 1 | -0/+16 |
| 2021-12-21 | [GlobalISel] Verify operand types for G_SHL, G_LSHR, G_ASHR | Jay Foad | 2 | -1/+22 |
| 2021-12-05 | [GlobalISel] Allow DBG_VALUE to use undefined vregs before LiveDebugValues. | Jack Andersen | 2 | -0/+78 |
| 2021-09-02 | Revert @llvm.isnan intrinsic patchset. | Roman Lebedev | 1 | -33/+0 |
| 2021-08-20 | [GlobalISel] Add G_LLROUND | Jessica Paquette | 2 | -2/+25 |
| 2021-08-19 | [GlobalISel] Add a G_LROUND instruction | Jessica Paquette | 1 | -0/+23 |
| 2021-08-19 | [AArch64][GlobalISel] Add G_VECREDUCE fewerElements support for full scalariz... | Amara Emerson | 1 | -2/+0 |
| 2021-08-18 | [GlobalISel] Add G_ISNAN | Jessica Paquette | 1 | -0/+33 |
