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AgeCommit message (Expand)AuthorFilesLines
2023-12-11[GlobalISel] Add G_PREFETCH (#74863)Jay Foad1-0/+40
2023-11-30MachineVerifier: Reject extra non-register operands on instructions (#73758)Matt Arsenault1-0/+30
2023-11-07[MachineVerifier] Fix COPY check in MachineVerifier for scalable vectorsMichael Maitland1-2/+41
2023-11-07[CodeGen][MachineVerifier] Use TypeSize instead of unsigned for getRe… (#70...Michael Maitland1-0/+23
2023-10-30[GISel] Restrict G_BSWAP to multiples of 16 bits. (#70245)Craig Topper1-0/+19
2023-09-29[test] -march -> -mtriple (#67741)Visoiu Mistrih Francis2-2/+2
2023-09-29[test] Change llc -march=aarch64|arm64 to -mtriple=aarch64|arm64Fangrui Song41-41/+41
2023-09-01MachineVerifier: Add tests which are incorrectly acceptedMatt Arsenault3-0/+64
2023-08-21[AArch64] Update generic sched model to A510Harvin Iriawan1-1/+1
2023-04-18[X86] Fix checks for illegal physreg COPY instructionsJay Foad1-3/+11
2023-02-14[PowerPC][GISel] add support for fpconstantChen Zheng1-0/+40
2022-12-07[GlobalISel] Add a new G_INVOKE_REGION_START instruction to fix an EH bug.Amara Emerson1-0/+22
2022-11-17[GlobalISel] Better verification of G_UNMERGE_VALUESJay Foad1-0/+33
2022-11-15[GlobalISel] Remove semantic operand of G_IS_FPCLASSSerge Pavlov1-10/+7
2022-09-22[GlobalISel] Enforce G_ASSERT_ALIGN to have a valid alignment > 0.Amara Emerson1-0/+17
2022-09-22MachineVerifier: Verify REG_SEQUENCEMatt Arsenault1-0/+59
2022-09-05[MachineVerifier] Fix crash on early clobbered subreg operands.Daniil Fukalov1-0/+31
2022-08-19[MachineVerifier] add checks for INLINEASM_BRNick Desaulniers1-0/+178
2022-05-27[GlobalISel] Add G_IS_FPCLASSSerge Pavlov1-0/+40
2022-04-22GlobalISel: Relax handling of G_ASSERT_* with source register classesMatt Arsenault2-16/+18
2022-04-11GlobalISel: Verify atomic load/store ordering restrictionMatt Arsenault2-0/+12
2022-04-05MachineVerifier: Diagnose undef set on full register defsMatt Arsenault1-0/+16
2021-12-21[GlobalISel] Verify operand types for G_SHL, G_LSHR, G_ASHRJay Foad2-1/+22
2021-12-05[GlobalISel] Allow DBG_VALUE to use undefined vregs before LiveDebugValues.Jack Andersen2-0/+78
2021-09-02Revert @llvm.isnan intrinsic patchset.Roman Lebedev1-33/+0
2021-08-20[GlobalISel] Add G_LLROUNDJessica Paquette2-2/+25
2021-08-19[GlobalISel] Add a G_LROUND instructionJessica Paquette1-0/+23
2021-08-19[AArch64][GlobalISel] Add G_VECREDUCE fewerElements support for full scalariz...Amara Emerson1-2/+0
2021-08-18[GlobalISel] Add G_ISNANJessica Paquette1-0/+33
2021-08-10[X86] AVX512FP16 instructions enabling 1/6Wang, Pengfei1-2/+2
2021-07-21[MachineVerifier] Make INSERT_SUBREG diagnostic respect operand 2 subregsJon Roelofs1-1/+6
2021-07-20[MachineVerifier] Diagnose invalid INSERT_SUBREGsJon Roelofs1-0/+31
2021-07-16Revert "[MachineVerifier] Diagnose invalid INSERT_SUBREGs"Jon Roelofs1-29/+0
2021-07-16[MachineVerifier] Diagnose invalid INSERT_SUBREGsJon Roelofs1-0/+29
2021-06-30CodeGen: Print/parse LLTs in MachineMemOperandsMatt Arsenault9-34/+34
2021-06-30[GISel] Support llvm.memcpy.inlineJon Roelofs4-1/+112
2021-04-28GlobalISel: Relax verification of physical register copy typesMatt Arsenault1-0/+54
2021-03-25[GlobalISel] Add G_ROTR and G_ROTL opcodes for rotates.Amara Emerson1-0/+13
2021-03-25[AArch64][GlobalISel] Emit bzero on DarwinJessica Paquette1-0/+33
2021-03-24Add missing -march to runline in llvm/test/MachineVerifier/test_g_ubfx_sbfx.mirJessica Paquette1-1/+1
2021-03-19[GlobalISel] Add G_SBFX + G_UBFX (bitfield extraction opcodes)Jessica Paquette1-0/+15
2021-03-01GlobalISel: Verify G_CONCAT_VECTORS has at least 2 sourcesMatt Arsenault1-16/+12
2021-02-17[GlobalISel] Add G_ASSERT_SEXTJessica Paquette2-0/+77
2021-02-12[GlobalISel] Simpler verification of G_SEXT_INREG and G_ASSERT_ZEXTJay Foad2-6/+2
2021-01-28[GlobalISel] Add G_ASSERT_ZEXTJessica Paquette2-0/+79
2021-01-13[Verifier] Add tied-ness verification to statepoint intsructionSerguei Katkov1-0/+30
2020-10-15[GlobalISel] Remove scalar src from non-sequential fadd/fmul reductions.Amara Emerson1-2/+2
2020-10-08[GlobalISel] Add G_VECREDUCE_* opcodes for vector reductions.Amara Emerson1-0/+35
2020-08-27[Test] Tidy up loose ends from LLVM_HAS_GLOBAL_ISELRussell Gallop25-25/+25
2020-08-27Fix for PS4 bots after 0b7f6cc71a72a85f8a0cbee836a7a8e31876951aRussell Gallop2-0/+2
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