| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-02-21 | [TargetLowering] Correctly yield NaN from FP_TO_BF16 | David Majnemer | 6 | -962/+962 |
| 2024-02-21 | [TargetLowering] Actually add the adjustment to the significand | David Majnemer | 1 | -28/+32 |
| 2024-02-21 | Correctly round FP -> BF16 when SDAG expands such nodes (#82399) | David Majnemer | 10 | -4421/+16961 |
| 2024-02-22 | [RISCV] Add test case for miscompile in gather -> strided load combine. NFC | Luke Lau | 1 | -0/+47 |
| 2024-02-21 | [SystemZ] Use VT (not ArgVT) for SlotVT in LowerCall(). (#82475) | Jonas Paulsson | 1 | -0/+18 |
| 2024-02-21 | [AArch64][SVE2] Enable dynamic shuffle for fixed length types. (#72490) | Dinar Temirbulatov | 1 | -24/+383 |
| 2024-02-21 | [AArch64] Fix stack probing clobbering flags (#81879) | Momchil Velikov | 1 | -0/+107 |
| 2024-02-21 | [X86] LowerCTPOP - add i3 and i4 LUT 'shift+mask' expansions | Simon Pilgrim | 1 | -37/+38 |
| 2024-02-21 | [X86] LowerCTPOP - "ctpop(i2 x) --> sub(x, (x >> 1))" | Simon Pilgrim | 1 | -25/+19 |
| 2024-02-21 | [AArch64][GlobalISel] Refactor BITCAST Legalization (#80505) | chuongg3 | 2 | -172/+239 |
| 2024-02-21 | [LoongArch] Assume no-op addrspacecasts by default (#82332) | hev | 1 | -0/+47 |
| 2024-02-21 | [RISCV][ISel] Combine vector fadd/fsub/fmul with fp extend. (#81248) | Chia | 4 | -25/+99 |
| 2024-02-21 | [X86] Regenerate vector tests to add missing avx512 constant broadcast comments | Simon Pilgrim | 4 | -14/+14 |
| 2024-02-21 | [X86] Regenerate saddsat/ssubsat vector tests | Simon Pilgrim | 2 | -2/+2 |
| 2024-02-21 | [GlobalISel] replace right identity X * -1.0 with fneg(x) (#80526) | Nick Anderson | 3 | -152/+244 |
| 2024-02-21 | [AArch64][GlobalISel] Pre-Commit Tests for Refactor BITCAST | Tuan Chuong Goh | 1 | -9/+499 |
| 2024-02-21 | [RISCV][SDAG] Fold `select c, ~x, x` into `xor -c, x` (#82462) | Yingwei Zheng | 1 | -0/+177 |
| 2024-02-21 | [GlobalISel] Clamp out-of-range G_EXTRACT_VECTOR_ELT constant indices when co... | Owen Anderson | 1 | -0/+38 |
| 2024-02-21 | Revert "Implement convergence control in MIR using SelectionDAG (#71785)" | Sameer Sahasrabuddhe | 13 | -193/+67 |
| 2024-02-21 | [RISCV] Support llvm.readsteadycounter intrinsic | Wang Pengcheng | 1 | -0/+28 |
| 2024-02-21 | Implement convergence control in MIR using SelectionDAG (#71785) | Sameer Sahasrabuddhe | 13 | -67/+193 |
| 2024-02-20 | [SPIR-V] Fix vloadn OpenCL builtin lowering (#81148) | Michal Paszkowski | 3 | -95/+71 |
| 2024-02-20 | [GlobalISel] Make sure to check for load barriers when merging G_EXTRACT_VECT... | Owen Anderson | 1 | -0/+46 |
| 2024-02-20 | [Hexagon] Update InstrInfo to include LD/ST offsets of vector instructions (#... | Sumanth Gundapaneni | 1 | -0/+59 |
| 2024-02-20 | [AMDGPU] Use autogenerated test checks for sdwa-preserve.mir test. NFC. (#82380) | Valery Pykhtin | 1 | -31/+49 |
| 2024-02-21 | [WebAssembly] Add segment RETAIN flag to support private retained data (#81539) | Yuta Saito | 1 | -0/+22 |
| 2024-02-20 | Revert "[AArch64] Restore Z-registers before P-registers (#79623)" | Caroline Concatto | 11 | -167/+167 |
| 2024-02-20 | Revert "[AArch64] Remove unused ReverseCSRRestoreSeq option. (#82326)" | Caroline Concatto | 1 | -0/+101 |
| 2024-02-20 | [X86] computeKnownBitsForTargetNode - add generic handling of PSHUFB | Simon Pilgrim | 1 | -205/+178 |
| 2024-02-20 | [X86] Fold add(psadbw(X,0),psadbw(Y,0)) -> psadbw(add(X,Y),0) | Simon Pilgrim | 1 | -38/+30 |
| 2024-02-20 | [AArch64] Remove unused ReverseCSRRestoreSeq option. (#82326) | Sander de Smalen | 1 | -101/+0 |
| 2024-02-20 | [XCOFF] Support the subtype flag in DWARF section headers (#81667) | stephenpeckham | 1 | -0/+3 |
| 2024-02-20 | [AMDGPU] Fix operand types for `V_DOT2_F32_BF16` (#82044) | Shilei Tian | 1 | -7/+7 |
| 2024-02-20 | Revert "[Hexagon] Optimize post-increment load and stores in loops. (#82011)" | Krasimir Georgiev | 5 | -690/+0 |
| 2024-02-20 | [AArch64][AMDGPU][GlobalISel] Remove vector handling from unmerge_dead_to_tru... | David Green | 22 | -419/+261 |
| 2024-02-20 | [GlobalIsel] Combine logic of floating point compares (#81886) | Thorsten Schütt | 1 | -0/+146 |
| 2024-02-20 | [RISCV] Select pattern (shl (sext_vl/zext_vl), 1) to VWADD/VWADDU. (#82225) | Yeting Kuo | 1 | -16/+116 |
| 2024-02-19 | [RISCV][GISEL] Add IRTranslation for insertelement with scalable vector type ... | Michael Maitland | 1 | -0/+1947 |
| 2024-02-19 | Add support for the SPIR-V extension SPV_KHR_uniform_group_instructions (#82064) | Vyacheslav Levytskyy | 1 | -0/+80 |
| 2024-02-19 | [DAGCombiner] Preserve nneg flag from inner zext when we combine (z/s/aext (z... | Craig Topper | 1 | -54/+21 |
| 2024-02-19 | fix generation of unnecessary OpExecutionMode records (#81839) | Vyacheslav Levytskyy | 1 | -0/+39 |
| 2024-02-19 | [RISCV] Add more zext nneg tests. NFC | Craig Topper | 1 | -0/+82 |
| 2024-02-19 | [DAGCombiner][RISCV] Optimize (zext nneg (truncate X)) if X has known sign bi... | Craig Topper | 2 | -25/+8 |
| 2024-02-19 | [RISCV] Add test cases for missed opportunites to treat a zext nneg as sext. NFC | Craig Topper | 1 | -0/+87 |
| 2024-02-19 | [X86] psadbw.ll - add AVX2 target test coverage | Simon Pilgrim | 1 | -90/+134 |
| 2024-02-19 | [X86] Add some basic test coverage for #81765 | Simon Pilgrim | 1 | -2/+103 |
| 2024-02-19 | [AArch64] Restore Z-registers before P-registers (#79623) | CarolineConcatto | 11 | -167/+167 |
| 2024-02-19 | Add support for atomic instruction on floating-point numbers (#81683) | Vyacheslav Levytskyy | 6 | -0/+267 |
| 2024-02-19 | [AArch64] Fix wrong condition in `canUseAsPrologue` (#81878) | Momchil Velikov | 1 | -0/+105 |
| 2024-02-19 | arm64_32: extend @llvm.stackguard call to in-DAG 64-bits before handing off | Tim Northover | 1 | -0/+14 |
