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path: root/llvm/test/CodeGen/VE
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2024-02-19[DAGCombiner][RISCV] Optimize (zext nneg (truncate X)) if X has known sign bi...Craig Topper1-2/+0
2024-02-05[CodeGen] Convert tests to opaque pointers (NFC)Nikita Popov2-8/+8
2023-10-24BlockFrequencyInfoImpl: Avoid big numbers, increase precision for small spreadsMatthias Braun2-87/+89
2023-10-09Revert "[CodeGen] Really renumber slot indexes before register allocation (#6...Jay Foad3-387/+386
2023-10-09[CodeGen] Really renumber slot indexes before register allocation (#67038)Jay Foad3-386/+387
2023-08-18[DAG] SimplifyDemandedBits - if we're only demanding the msb, a UMIN/UMAX nod...Simon Pilgrim2-4/+2
2023-08-18[VE] Change the way of lowering storeKazushi (Jam) Marukawa1-1/+13
2023-08-17[VE] Avoid vectorizing store/load in scalar modeKazushi (Jam) Marukawa1-0/+32
2023-06-26[SelectionDAG] Improve expansion of wide min/maxEli Friedman4-58/+78
2023-06-14[NFC] Regenerate several VE codegen tests.Amaury Séchet4-119/+555
2023-05-23[LegalizeTypes][ARM][AArch6][RISCV][VE][WebAssembly] Add special case for smi...Craig Topper1-8/+2
2023-05-17[NFC][Py Reformat] Reformat lit.local.cfg python files in llvmTobias Hieta2-2/+2
2023-05-12[DAGCombiner][AArch64][VE] Teach BuildUDIV/SDIV to use 2x mul when mulh/mul_l...Craig Topper3-19/+42
2023-04-26VE: Register null MCTargetStreamerMatt Arsenault1-0/+5
2023-02-09[SelectionDAG] Do not second-guess alignment for allocaAndrew Savonichev3-21/+21
2023-01-24IR: Add atomicrmw uinc_wrap and udec_wrapMatt Arsenault1-0/+240
2022-12-23[VE] Convert test to opaque pointers (NFC)Nikita Popov1-559/+527
2022-12-23[VE] Name instructions in test (NFC)Nikita Popov1-1000/+1055
2022-12-19[VE] Convert some tests to opaque pointers (NFC)Nikita Popov78-2352/+2136
2022-12-15Revert "[SelectionDAG] Do not second-guess alignment for alloca"Ron Lieberman3-21/+21
2022-12-15[SelectionDAG] Do not second-guess alignment for allocaAndrew Savonichev3-21/+21
2022-11-15[SDAG] avoid udiv/urem transform for vector/scalar type mismatchesSanjay Patel1-0/+45
2022-10-20[VE] Change the way to lower selectccKazushi (Jam) Marukawa22-503/+350
2022-10-15[CodeGen] Using ZExt for extractelement indices.Peter Rong2-3/+23
2022-10-15[VE] Change the way to lower selectKazushi (Jam) Marukawa2-28/+0
2022-09-28AtomicExpand: Use llvm.ptrmask instead of ptrtointMatt Arsenault1-81/+73
2022-09-27[VE] Change to expand FPOWKazushi (Jam) Marukawa1-0/+256
2022-09-26[VE] Disable automatic maxnum/minnum selectionKazushi (Jam) Marukawa2-8/+217
2022-09-26[VE] Support smax/sminKazushi (Jam) Marukawa5-15/+1411
2022-09-21[VE] Add maxnum and minnumKazushi (Jam) Marukawa2-0/+324
2022-09-21[VE] Change to expand FMAKazushi (Jam) Marukawa1-0/+236
2022-09-20VE: Use generated checks for a copy-pasted output testMatt Arsenault1-109/+398
2022-09-16[VP][VE] Default VP_SREM/UREM to Expand and add generic expansion using VP_SD...Craig Topper2-20/+178
2022-09-12[LegalizeTypes] Improve splitting for urem/udiv by constant for some constants.Craig Topper1-2/+2
2022-08-24[update_llc_test_checks][VE] Handle .Lfoo$local in function regexAlex Richardson1-30/+0
2022-08-23[VE] Support inlineasm memory operandKazushi (Jam) Marukawa2-0/+31
2022-07-27[NFC] Automatically generate CodeGen/VE/Scalar/atomic.llAmaury Séchet1-20/+21
2022-07-19[VE] Support load/store/spill of vector mask registersKazushi (Jam) Marukawa2-0/+2444
2022-07-05[VE] Restructure eliminateFrameIndexKazushi (Jam) Marukawa2-0/+1603
2022-07-05Revert "[VE] Restructure eliminateFrameIndex"Kazushi (Jam) Marukawa2-1603/+0
2022-07-05[VE] Restructure eliminateFrameIndexKazushi (Jam) Marukawa2-0/+1603
2022-07-01[VE] Support load/store vm regsitersKazushi (Jam) Marukawa4-0/+343
2022-04-06Revert "[CodeGen] Place SDNode debug ID declaration under appropriate #if"Daniil Kovalev2-4/+4
2022-04-06[CodeGen] Place SDNode debug ID declaration under appropriate #ifDaniil Kovalev2-4/+4
2022-03-22[VP] Preserve address space of pointer for strided load/store intrinsics.Craig Topper2-32/+32
2022-03-16[VE] Remove output to /dev/stdoutJake Egan10-10/+10
2022-03-16[VE] v512|256 f32|64 fneg isel and testsSimon Moll2-0/+40
2022-03-15[VE] strided v256.23 isel and testsSimon Moll2-0/+328
2022-03-14[VE] v256f32|64 fma iselSimon Moll3-0/+283
2022-03-14[VE] Support more intrinsicsKazushi (Jam) Marukawa5-0/+791
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