aboutsummaryrefslogtreecommitdiff
path: root/llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
AgeCommit message (Expand)AuthorFilesLines
2023-10-24BlockFrequencyInfoImpl: Avoid big numbers, increase precision for small spreadsMatthias Braun1-45/+48
2023-10-09Revert "[CodeGen] Really renumber slot indexes before register allocation (#6...Jay Foad1-116/+112
2023-10-09[CodeGen] Really renumber slot indexes before register allocation (#67038)Jay Foad1-112/+116
2023-07-14[ARM] Adjust strd/ldrd codegen alignment requirementsMaurice Heumann1-20/+20
2023-07-12[SCEVExpander] Fix GEP IV inc reuse logic for opaque pointersNikita Popov1-11/+12
2023-07-09[CGP] Enable CodeGenPrepares phi type convertion.David Green1-107/+89
2023-07-07[CodeGen]Allow targets to use target specific COPY instructions for live rang...Yashwant Singh1-7/+8
2023-07-03Revert "[ARM] Adjust strd/ldrd codegen alignment requirements"David Spickett1-20/+20
2023-07-02[ARM] Adjust strd/ldrd codegen alignment requirementsMaurice Heumann1-20/+20
2023-05-25[CodeGen][ShrinkWrap] Enable PostShrinkWrap by defaultsgokhale1-8/+11
2023-05-08Revert "[CodeGen][ShrinkWrap] Split restore point"Alan Zhao1-11/+8
2023-05-08[CodeGen][ShrinkWrap] Split restore pointsgokhale1-8/+11
2023-04-13Revert "[CodeGen][ShrinkWrap] Split restore point"sgokhale1-11/+8
2023-04-11[CodeGen][ShrinkWrap] Split restore pointsgokhale1-8/+11
2023-04-04[Thumb2] Convert tests to opaque pointers (NFC)Nikita Popov1-565/+458
2023-04-04[Thumb2] Name instructions in tests (NFC)Nikita Popov1-681/+686
2023-01-18[AsmParser] Remove typed pointer auto-detectionNikita Popov1-1/+1
2022-09-26[ARM] Enable and/cmp0 foldingMomchil Velikov1-4/+3
2021-09-24Revert "Allow rematerialization of virtual reg uses"Stanislav Mekhanoshin1-48/+50
2021-09-09[SimplifyCFG] performBranchToCommonDestFolding(): require block-closed SSA fo...Roman Lebedev1-1/+1
2021-08-24Allow rematerialization of virtual reg usesStanislav Mekhanoshin1-50/+48
2021-08-18Revert "Allow rematerialization of virtual reg uses"Petr Hosek1-48/+50
2021-08-17[ARM] Enable subreg livenessDavid Green1-71/+65
2021-08-16Allow rematerialization of virtual reg usesStanislav Mekhanoshin1-50/+48
2021-06-11[CodeGen][regalloc] Don't align stack slots if the stack can't be realignedTomas Matheson1-20/+20
2021-05-13[ARM] Constrain CMPZ shift combine to a single useDavid Green1-4/+2
2021-05-06[ARM] Simplification to ARMBlockPlacement Pass.Malhar Jajoo1-29/+29
2021-04-12[ARM] Updates to arm-block-placement passMalhar Jajoo1-31/+29
2021-03-11[ARM] Improve WLS loweringDavid Green1-101/+98
2021-02-24[ARM] Expand the range of allowed post-incs in load/store optimizerDavid Green1-2/+1
2021-02-19Revert "[ARM] Expand the range of allowed post-incs in load/store optimizer"David Green1-1/+2
2021-02-18[ARM] Expand the range of allowed post-incs in load/store optimizerDavid Green1-2/+1
2021-02-15[ARM] Extend search for increment in load/store optimizerDavid Green1-4/+2
2021-02-14[ARM] A couple of small MVE reduction tests from intrinsics. NFCDavid Green1-0/+19
2021-02-08[ARM] Add some float Biquad cases showing difficult shuffling. NFCDavid Green1-0/+200
2021-02-02[ARM] Remove DLS lr, lrDavid Green1-1/+0
2021-01-25[ARM] Use half directly for args/return types in test. NFCDavid Green1-1/+1
2021-01-23[SimplifyCFG] FoldBranchToCommonDest(): re-lift restrictions on liveout uses ...Roman Lebedev1-33/+31
2021-01-18[ARM] Don't handle low overhead branches in AnalyzeBranchDavid Green1-45/+45
2021-01-16[ARM] Add low overhead loops terminators to AnalyzeBranchDavid Green1-45/+45
2020-12-14[NFCI][Thumb2] Regenerate MVE tests i missed in 59560e85897afc50090b6c3d920ba...Roman Lebedev1-31/+33
2020-12-10[ARM][RegAlloc] Add t2LoopEndDecDavid Green1-1/+1
2020-11-29[BasicAA] Generalize recursive phi alias analysisNikita Popov1-2/+2
2020-11-27Reland [SimplifyCFG] FoldBranchToCommonDest: lift use-restriction on bonus in...Roman Lebedev1-33/+31
2020-11-23[SelectionDAG][ARM][AArch64][Hexagon][RISCV][X86] Add SDNPCommutative to fma ...Craig Topper1-1/+1
2020-11-10[ARM] Add a RegAllocHint for hinting t2DoLoopStart towards LRDavid Green1-11/+12
2020-11-10[ARM] Alter t2DoLoopStart to define lrDavid Green1-35/+30
2020-11-03[MachineInstr] Add support for instructions with multiple memory operands.Michael Liao1-4/+4
2020-10-20Revert "[ARM][LowOverheadLoops] Adjust Start insertion."David Green1-3/+3
2020-10-01[ARM][LowOverheadLoops] Adjust Start insertion.Sam Parker1-3/+3
generated by cgit v1.1 at 2024-09-07 16:05:06 +0000