| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2023-12-05 | [RISCV] Support FrameIndex operands in getMemOperandsWithOffsetWidth / getMem... | Alex Bradbury | 1 | -22/+22 |
| 2023-12-05 | [RISCV] Allocate the varargs GPR save area as a single object. (#74354) | Craig Topper | 1 | -6/+6 |
| 2023-12-05 | [RISCV] Use iXLen for ptr<->int casts in vararg.ll. NFC | Craig Topper | 1 | -30/+13 |
| 2023-12-05 | [RISCV] Use iXLen for ptr<->int casts in vararg.ll (#74426) | Craig Topper | 1 | -39/+24 |
| 2023-10-06 | [RISCV] Strip W suffix from ADDIW (#68425) | Philip Reames | 1 | -4/+4 |
| 2023-08-10 | [RISCV] Enable alias analysis by default | Yunze Zhu | 1 | -0/+12 |
| 2023-03-27 | [RISCV] Move compressible registers to the beginning of the FP allocation order. | Craig Topper | 1 | -4/+4 |
| 2023-02-09 | [SelectionDAG] Do not second-guess alignment for alloca | Andrew Savonichev | 1 | -11/+11 |
| 2023-01-20 | [MachineCombiner] Use default latency model when no detailed model available | Philip Reames | 1 | -28/+28 |
| 2022-12-29 | [RISCV] Add integer scalar instructions to isAssociativeAndCommutative | Hsiangkai Wang | 1 | -28/+28 |
| 2022-12-28 | [RISCV] Prefer ADDI over ORI if the known bits are disjoint. | Craig Topper | 1 | -4/+4 |
| 2022-12-22 | [RISCV] Add pass to remove W suffix from ADDIW and SLLIW to improve compressi... | Nitin John Raj | 1 | -4/+4 |
| 2022-12-19 | [RISCV] Convert some tests to opaque pointers (NFC) | Nikita Popov | 1 | -115/+100 |
| 2022-12-15 | Revert "[SelectionDAG] Do not second-guess alignment for alloca" | Ron Lieberman | 1 | -9/+9 |
| 2022-12-15 | [SelectionDAG] Do not second-guess alignment for alloca | Andrew Savonichev | 1 | -9/+9 |
| 2022-12-02 | [RISCV] Fold low 12 bits into instruction during frame index elimination | Philip Reames | 1 | -48/+24 |
| 2022-11-30 | [RISCV] Share code for fixed offsets adjustRegs (thus materializing fewer con... | Philip Reames | 1 | -6/+6 |
| 2022-11-25 | [RISCV] Use register allocation hints to improve use of compressed instructions. | Craig Topper | 1 | -16/+16 |
| 2022-08-30 | [RISCV] Improve isel of AND with shiftedMask containing 32 leading zeros and ... | Craig Topper | 1 | -16/+8 |
| 2022-06-03 | [RISCV] Use SelectionDAG::isBaseWithConstantOffset in scalar load/store addre... | Craig Topper | 1 | -64/+58 |
| 2022-04-21 | [RISCV] Add special case to constant materialization to remove trailing zeros... | Craig Topper | 1 | -8/+6 |
| 2021-12-31 | [RISCV] Use constant pool for large integers | wangpc | 1 | -48/+12 |
| 2021-11-22 | [RISCV] Reverse the order of loading/storing callee-saved registers. | Hsiangkai Wang | 1 | -41/+41 |
| 2021-11-22 | [RISCV] Generate pseudo instruction li | wangpc | 1 | -80/+80 |
| 2021-08-18 | [RISCV] Insert sext_inreg when type legalizing add/sub/mul with constant LHS. | Craig Topper | 1 | -4/+4 |
| 2021-08-18 | [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits... | Craig Topper | 1 | -4/+4 |
| 2021-03-21 | [RISCV] remove redundant instruction when eliminate frame index | luxufan | 1 | -3/+0 |
| 2021-01-15 | [RISCV] Add implementation of targetShrinkDemandedConstant to optimize AND im... | Craig Topper | 1 | -8/+2 |
| 2021-01-14 | [RISCV][NFC] Regenerate Calling Convention Tests | Sam Elliott | 1 | -15/+15 |
| 2021-01-04 | [RISCV] Replace i32 with XLenVT in (add AddrFI, simm12) isel patterns. | Craig Topper | 1 | -32/+16 |
| 2020-12-09 | [RISCV][NFC] Regenerate RISCV CodeGen tests | Michael Munday | 1 | -189/+189 |
| 2020-08-27 | [RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move | Alex Richardson | 1 | -3/+3 |
| 2020-06-12 | [DAGCombine] Generalize the case (add (or x, c1), c2) -> (add x, (c1 + c2)) | Michael Liao | 1 | -20/+20 |
| 2020-04-15 | [SelectionDAG] Fix usage of Align constructing MachineMemOperands. | Eli Friedman | 1 | -3/+3 |
| 2020-02-10 | [RISCV] Fix incorrect FP base CFI offset for variable argument functions | Shiva Chen | 1 | -4/+4 |
| 2019-11-14 | [RISCV] Fix wrong CFI directives | Luís Marques | 1 | -22/+0 |
| 2019-11-13 | Revert "[RISCV] Fix wrong CFI directives" | Luís Marques | 1 | -0/+22 |
| 2019-11-13 | [RISCV] Fix wrong CFI directives | Luís Marques | 1 | -22/+0 |
| 2019-11-10 | [RISCV] Fix CFA when doing split sp adjustment with fp | Luís Marques | 1 | -6/+2 |
| 2019-11-10 | [RISCV][NFC] Add CFI-related tests | Luís Marques | 1 | -1/+263 |
| 2019-09-17 | [RISCV] Switch to the Machine Scheduler | Luis Marques | 1 | -129/+129 |
| 2019-09-17 | Revert Patch from Phabricator | Luis Marques | 1 | -129/+129 |
| 2019-09-17 | Patch from Phabricator | Luis Marques | 1 | -129/+129 |
| 2019-08-06 | [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensions | Shiva Chen | 1 | -2/+2 |
| 2019-03-30 | [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float... | Alex Bradbury | 1 | -5/+15 |
| 2019-03-30 | [RISCV] Add RV64 CHECK lines to test/CodeGen/RISCV/vararg.ll and prepare for ... | Alex Bradbury | 1 | -644/+1555 |
| 2019-03-30 | [RISCV][NFC] Remove floating point operations from test/CodeGen/RISCV/vararg.ll | Alex Bradbury | 1 | -65/+65 |
| 2019-03-13 | [RISCV] Only mark fp as reserved if the function has a dedicated frame pointer | Alex Bradbury | 1 | -4/+4 |
| 2019-01-25 | Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI | Ana Pazos | 1 | -10/+10 |
| 2019-01-14 | Replace "no-frame-pointer-*" function attributes with "frame-pointer" | Francis Visoiu Mistrih | 1 | -1/+1 |
