| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2023-10-09 | Revert "[CodeGen] Really renumber slot indexes before register allocation (#6... | Jay Foad | 1 | -28/+28 |
| 2023-10-09 | [CodeGen] Really renumber slot indexes before register allocation (#67038) | Jay Foad | 1 | -28/+28 |
| 2023-09-19 | [CodeGen] Renumber slot indexes before register allocation (#66334) | Jay Foad | 1 | -28/+28 |
| 2023-06-13 | [DAGCombine] Make sure combined nodes are added back to the worklist in topol... | Amaury Séchet | 1 | -8/+6 |
| 2023-06-05 | Revert "[DAGCombine] Make sure combined nodes are added back to the worklist ... | JP Lehr | 1 | -6/+8 |
| 2023-06-05 | [DAGCombine] Make sure combined nodes are added back to the worklist in topol... | Amaury Séchet | 1 | -8/+6 |
| 2023-04-15 | [RISCV] Optimize multiplication with immediates | Ben Shi | 1 | -18/+18 |
| 2023-01-20 | [MachineCombiner] Use default latency model when no detailed model available | Philip Reames | 1 | -81/+81 |
| 2023-01-13 | [MachineCombiner] Lift same-bb restriction for reassociable ops. | Florian Hahn | 1 | -2/+2 |
| 2022-12-29 | [RISCV] Add integer scalar instructions to isAssociativeAndCommutative | Hsiangkai Wang | 1 | -102/+102 |
| 2022-12-22 | [RISCV] Add pass to remove W suffix from ADDIW and SLLIW to improve compressi... | Nitin John Raj | 1 | -36/+36 |
| 2022-12-06 | [RISCV] Teach RISCVMatInt to prefer li+slli over lui+addi(w) for compressibil... | Craig Topper | 1 | -38/+38 |
| 2022-12-01 | [RISCV] Add ADDW/AND/OR/XOR/SUB/SUBW to getRegAllocHints. | Craig Topper | 1 | -32/+32 |
| 2022-11-25 | [RISCV] Add ADD to getRegAllocationHints to improve to improve use of c.add. | Craig Topper | 1 | -12/+12 |
| 2022-10-24 | [RISCV] Add ORI to hasAllNBitUsers. | Craig Topper | 1 | -0/+68 |
| 2022-10-22 | Revert "[DAGCombiner] Fold (mul (sra X, BW-1), Y) -> (neg (and (sra X, BW-1),... | Craig Topper | 1 | -5/+5 |
| 2022-10-22 | [DAGCombiner] Fold (mul (sra X, BW-1), Y) -> (neg (and (sra X, BW-1), Y)) | Craig Topper | 1 | -5/+5 |
| 2022-10-11 | Revert "[DAGCombiner] Fold (mul (sra X, BW-1), Y) -> (neg (and (sra X, BW-1),... | Craig Topper | 1 | -5/+5 |
| 2022-10-11 | [DAGCombiner] Fold (mul (sra X, BW-1), Y) -> (neg (and (sra X, BW-1), Y)) | Craig Topper | 1 | -5/+5 |
| 2022-08-10 | [RISCV] Implement isUsedByReturnOnly TargetLowering hook in order to tailcall... | Alex Bradbury | 1 | -30/+5 |
| 2022-06-15 | [SelectionDAG] fold 'Op0 - (X * MulC)' to 'Op0 + (X << log2(-MulC))' | Ping Deng | 1 | -26/+8 |
| 2022-06-15 | [RISCV][NFC] Add more tests for instruction selection of 'mul' | Ping Deng | 1 | -0/+52 |
| 2022-02-23 | [DAG] try to convert multiply to shift via demanded bits | Sanjay Patel | 1 | -26/+8 |
| 2022-02-20 | [AArch64][RISCV][x86] add tests for mul-add demanded bits; NFC | Sanjay Patel | 1 | -0/+51 |
| 2022-01-21 | [RISCV] Set CostPerUse to 1 iff RVC is enabled | wangpc | 1 | -195/+193 |
| 2021-11-22 | [RISCV] Reverse the order of loading/storing callee-saved registers. | Hsiangkai Wang | 1 | -13/+13 |
| 2021-11-22 | [RISCV] Generate pseudo instruction li | wangpc | 1 | -31/+31 |
| 2021-09-24 | Revert "Allow rematerialization of virtual reg uses" | Stanislav Mekhanoshin | 1 | -35/+37 |
| 2021-08-31 | [RISCVISelLowering] avoid emitting libcalls to __mulodi4() and __multi3() | Nick Desaulniers | 1 | -104/+221 |
| 2021-08-26 | [RISCV] Insert a sext_inreg when type legalizing i32 shl by constant on RV64. | Craig Topper | 1 | -2/+2 |
| 2021-08-18 | [RISCV] Insert sext_inreg when type legalizing add/sub/mul with constant LHS. | Craig Topper | 1 | -3/+3 |
| 2021-08-18 | [RISCV] Teach isel to select ADDW/SUBW/MULW/SLLIW when only the lower 32-bits... | Craig Topper | 1 | -24/+24 |
| 2021-04-01 | [RISCV] Add custom type legalization to form MULHSU when possible. | Craig Topper | 1 | -8/+2 |
| 2021-04-01 | [RISCV] Add MULHU and MULHS tests with a constant operand. | Craig Topper | 1 | -4/+133 |
| 2021-03-28 | [RISCV] Add a RV64 mulhsu test case. NFC | Craig Topper | 1 | -0/+76 |
| 2021-03-28 | [RISCV] Add test case for mulhsu. | Craig Topper | 1 | -4/+55 |
| 2021-01-09 | [RISCV] Optimize multiplication with constant | Ben Shi | 1 | -205/+209 |
| 2021-01-06 | [RISCV][NFC] Add new test cases for mul | Ben Shi | 1 | -0/+204 |
| 2020-12-21 | [RISCV][NFC] Add tests for multiplication with constant | Ben Shi | 1 | -0/+410 |
| 2020-12-09 | [RISCV][NFC] Regenerate RISCV CodeGen tests | Michael Munday | 1 | -30/+30 |
| 2020-07-07 | [RISCV] Optimize multiplication by constant | Ben Shi | 1 | -146/+101 |
| 2020-07-01 | [RISCV][NFC] Pre-commit tests for D82660 | Ben Shi | 1 | -0/+306 |
| 2019-09-17 | [RISCV] Switch to the Machine Scheduler | Luis Marques | 1 | -1/+1 |
| 2019-09-17 | Revert Patch from Phabricator | Luis Marques | 1 | -1/+1 |
| 2019-09-17 | Patch from Phabricator | Luis Marques | 1 | -1/+1 |
| 2019-01-12 | [RISCV] Introduce codegen patterns for RV64M-only instructions | Alex Bradbury | 1 | -4/+132 |
| 2018-04-25 | [RISCV] Expand function call to "call" pseudoinstruction | Shiva Chen | 1 | -21/+7 |
| 2018-01-18 | [RISCV] Codegen support for the standard RV32M instruction set extension | Alex Bradbury | 1 | -1/+99 |
| 2018-01-18 | [RISCV] Implement frame pointer elimination | Alex Bradbury | 1 | -22/+0 |
| 2018-01-18 | [RISCV][NFC] Add nounwind to functions in div.ll and mul.ll | Alex Bradbury | 1 | -6/+6 |
