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path: root/llvm/test/CodeGen/RISCV/inline-asm-f-constraint-f.ll
AgeCommit message (Expand)AuthorFilesLines
2023-03-27[RISCV] Move compressible registers to the beginning of the FP allocation order.Craig Topper1-8/+8
2022-12-19[RISCV] Convert some tests to opaque pointers (NFC)Nikita Popov1-2/+2
2022-03-02[RISCV] More correctly ignore Zfinx register classes in getRegForInlineAsmCon...Craig Topper1-0/+20
2022-02-24[RISCV] Update computeTargetABI from llc as well as clangZakk Chen1-4/+5
2022-01-14[RISCV] Honor the VT when converting float point register names to register c...Craig Topper1-52/+2
2022-01-13[RISCV] Remove unused check prefixes. NFCCraig Topper1-21/+0
2022-01-13[RISCV] Add inline asm f32 test cases with D extension. NFCCraig Topper1-0/+75
2019-09-17[RISCV] Switch to the Machine SchedulerLuis Marques1-12/+12
2019-09-17Revert Patch from PhabricatorLuis Marques1-12/+12
2019-09-17Patch from PhabricatorLuis Marques1-12/+12
2019-08-08[RISCV] Allow ABI Names in Inline Assembly ConstraintsSam Elliott1-0/+27
2019-07-31[RISCV] Support 'f' Inline Assembly ConstraintSam Elliott1-0/+34
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