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path: root/llvm/test/CodeGen/RISCV/double-convert.ll
AgeCommit message (Expand)AuthorFilesLines
2023-10-09Revert "[CodeGen] Really renumber slot indexes before register allocation (#6...Jay Foad1-18/+18
2023-10-09[CodeGen] Really renumber slot indexes before register allocation (#67038)Jay Foad1-18/+18
2023-10-06[RISCV] Strip W suffix from ADDIW (#68425)Philip Reames1-11/+11
2023-05-25[RISCV][CodeGen] Support Zdinx on RV32 codegenShao-Ce SUN1-0/+493
2023-05-04[RISCV][CodeGen] Support Zdinx on RV64 codegenShao-Ce SUN1-0/+241
2023-04-29[TargetLowering] Don't use ISD::SELECT_CC in expandFP_TO_INT_SAT.Craig Topper1-101/+55
2023-03-27[RISCV] Move compressible registers to the beginning of the FP allocation order.Craig Topper1-66/+66
2023-03-16[RISCV]Optimize (riscvisd::select_cc x, 0, ne, x, 1)LiaoChunyu1-12/+6
2022-12-19[RISCV] Convert some tests to opaque pointers (NFC)Nikita Popov1-9/+9
2022-12-14[RISCV][CodeGen][SelectionDAG] Recursively check hasAllNBitUsers for logical ...Nitin John Raj1-5/+5
2022-11-25[RISCV] Use register allocation hints to improve use of compressed instructions.Craig Topper1-44/+32
2022-10-18[RISCV] Optimize SELECT_CC when the true value of select is ConstantLiaoChunyu1-115/+116
2022-10-13[RISCV] Match (select C, -1, X)->(or -C, X) during lowerSelectCraig Topper1-129/+110
2022-10-12[RISCV] Use branchless form for selects with 0 in either armPhilip Reames1-319/+279
2022-10-06[RISCV] Use branchless form for selects with -1 in either armPhilip Reames1-198/+140
2022-09-21Add all constant physical registers to callee preserved masksAlex Richardson1-3/+3
2022-09-13[RISCV] Fix a bug in i32 FP_TO_UINT_SAT lowering on RV64.Craig Topper1-16/+38
2022-09-12[RISCV] Add test cases with result of fp_to_s/uint_sat sign/zero-extended fro...Craig Topper1-0/+216
2022-08-01[RISCV] Explicitly select second operand of branch condition to X0.Craig Topper1-151/+149
2022-06-06[RISCV] Use check-prefixes to reduce check linesShao-Ce SUN1-156/+72
2022-02-04[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.Craig Topper1-50/+30
2022-01-21[RISCV] Set CostPerUse to 1 iff RVC is enabledwangpc1-93/+93
2022-01-10[RISCV] Use FP ABI on some of the FP tests to reduce the number of CHECK line...Craig Topper1-306/+142
2022-01-09[SelectionDAG] Add FP_TO_UINT_SAT/FP_TO_SINT_SAT to computeKnownBits/computeN...Craig Topper1-24/+6
2022-01-08[RISCV] Add i8/i16 fptosi/fptoui and fptosi_sat/fptoui_sat tests. NFCCraig Topper1-0/+699
2022-01-08[RISCV] Add nounwind to remove some cfi directives from test CHECKs. NFCCraig Topper1-24/+3
2021-12-18[RISCV] Remove stale comments from tests. NFCCraig Topper1-2/+0
2021-11-22[RISCV] Reverse the order of loading/storing callee-saved registers.Hsiangkai Wang1-49/+49
2021-11-22[RISCV] Generate pseudo instruction liwangpc1-54/+54
2021-11-11[RISCV] Add rv32i/rv64i command lines to some floating point tests. NFCCraig Topper1-0/+902
2021-09-22[RISCV] Remove stale FIXMEs from float-convert.ll and double-convert.ll. NFCCraig Topper1-1/+0
2021-09-22[RISCV] Add fcvt.s.w(u)/fcvt.d.w(u)/fcvt.h.w(u) to hasAllNBitUsersCraig Topper1-4/+1
2021-09-22[RISCV] Add test cases showing failure to use ADDIW before fcvt.s.w/fcvt.d.w/...Craig Topper1-0/+45
2021-08-07[RISCV] Support FP_TO_S/UINT_SAT for i32 and i64.Craig Topper1-61/+23
2021-07-24[RISCV] Custom lower (i32 (fptoui/fptosi X)).Craig Topper1-3/+3
2021-07-19[RISCV] Add test cases to show an issue with our fcvt.wu isel patterns on RV64.Craig Topper1-66/+102
2021-06-10[RISCV] Use ComputeNumSignBits/MaskedValueIsZero in RISCVDAGToDAGISel::select...Craig Topper1-2/+2
2021-06-10[RISCV] Add test cases that show failure to use some W instructions if they a...Craig Topper1-62/+108
2021-04-22[RISCV] Fix crash with fptosi.sat/fptoui.sat intrinsics on RV64. Add test cases.Craig Topper1-0/+241
2021-01-24[RISCV] Use bitsLE instead of strict == MVT::i32 in assertsexti32 and assertz...Craig Topper1-4/+4
2021-01-24[RISCV] Add test cases for missed opportunities to use fcvt.*.w(u) instructio...Craig Topper1-0/+80
2020-12-09[RISCV][NFC] Regenerate RISCV CodeGen testsMichael Munday1-12/+12
2019-09-17[RISCV] Switch to the Machine SchedulerLuis Marques1-3/+3
2019-09-17Revert Patch from PhabricatorLuis Marques1-3/+3
2019-09-17Patch from PhabricatorLuis Marques1-3/+3
2019-02-01[RISCV] Implement RV64D codegenAlex Bradbury1-0/+180
2018-04-12[RISCV] Codegen support for RV32D floating point conversion operationsAlex Bradbury1-0/+89
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