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AgeCommit message (Expand)AuthorFilesLines
2024-03-15[AVR] Remove earlyclobber from LDDRdPtrQ (#85277)Patryk Wychowaniec1-0/+163
2024-02-05[AVR] Convert tests to opaque pointers (NFC)Nikita Popov53-583/+573
2023-10-09Revert "[CodeGen] Really renumber slot indexes before register allocation (#6...Jay Foad1-9/+9
2023-10-09[CodeGen] Really renumber slot indexes before register allocation (#67038)Jay Foad1-9/+9
2023-10-02[AVR] Fix a crash in AVRInstrInfo::insertIndirectBranch (#67324)Ben Shi2-4/+47
2023-09-15[RA] Split a virtual register in cold blocks if it is not assigned preferred ...Guozhi Wei1-3/+2
2023-09-11[test] Change llc -march= to -mtriple=Fangrui Song4-8/+8
2023-07-24[CodeGen] Add machine verification to some testsJay Foad1-1/+1
2023-07-19[AVR] Expand shifts of all types except int8 and int16Patryk Wychowaniec2-37/+134
2023-07-19[AVR] Enable verifyInstructionPredicates for AVRJianjian GUAN1-1/+1
2023-06-11[AVR] Optimize 8-bit rotation when rotation bits == 3Ben Shi1-15/+7
2023-06-11[AVR] Optimize 8-bit rotation when rotation bits >= 4Ben Shi1-55/+7
2023-06-11[AVR] Fix incorrect expansion of pseudo instruction ROLBRdBen Shi3-41/+82
2023-06-11[AVR] Enable sub register livenessBen Shi2-11/+5
2023-06-11[AVR][NFC] Improve CodeGen testsBen Shi1-15/+26
2023-06-06[AVR][NFC][test] Supplement more tests of 8-bit rotationBen Shi1-8/+104
2023-06-04[AVR][NFC][test] Suppement a test of the pseudo instruction RORBRdBen Shi1-0/+25
2023-06-04[AVR] Fix incorrect operands of pseudo instruction 'ROLBRd'Patryk Wychowaniec2-6/+231
2023-05-17[NFC][Py Reformat] Reformat lit.local.cfg python files in llvmTobias Hieta1-1/+1
2023-04-17[AVR] Fix an issue of writing 16-bit portsBen Shi17-80/+115
2023-04-12[AVR] Disable post increment load from program memory spaceBen Shi1-0/+15
2023-04-10[AVR][NFC] Fix errors in commit 6e57f68e41c92936b9ef3a4e6fb286e8805a9fbcBen Shi1-3/+4
2023-04-10[AVR] Reject invalid LDD instruction with explicit errorBen Shi1-1/+8
2023-04-06[AVR] Fix incorrect expansion of pseudo instructions LPMWRdZ/ELPMWRdZBen Shi2-2/+195
2023-03-30[TwoAddressInstruction] Improve tests for register killed by instructionJay Foad1-1/+1
2023-03-24[AVR] Do not emit 'LPM Rd, Z' on devices without FeatureLPMXBen Shi2-0/+98
2023-03-21[AVR] Fix incorrect expansion of the pseudo 'ELPMBRdZ' instructionBen Shi2-4/+95
2023-02-28[AVR] Fix incorrect flags of livein registers when spilling themBen Shi1-0/+135
2023-02-09[AVR] Optimize 16-bit comparison with a constantBen Shi1-0/+96
2023-01-24[AVR] Support most address space castsAyke van Laethem1-0/+65
2023-01-23[AVR] Emit 'eicall' for devices with large program memoryBen Shi1-0/+30
2023-01-20[AVR] Fix incorrectly printed global symbol operands in inline-asmBen Shi1-17/+43
2023-01-13[AVR] Fix a bug in AsmPrinter when printing inline-asm operandsBen Shi1-0/+5
2023-01-08[AVR] Optimize 32-bit shifts: optimize REG_SEQUENCEAyke van Laethem1-45/+34
2023-01-08[AVR] Optimize 32-bit shifts: reverse shift + moveAyke van Laethem1-0/+211
2023-01-08[AVR] Optimize 32-bit shifts: shift by 4 bitsAyke van Laethem1-0/+134
2023-01-08[AVR] Optimize 32-bit shift: move bytes aroundAyke van Laethem1-0/+114
2023-01-08[AVR] Custom lower 32-bit shift instructionsAyke van Laethem1-0/+129
2023-01-08[SelectionDAG][AVR] Add support for lrint and lround intrinsicsAyke van Laethem4-0/+150
2023-01-08[AVR] correctly declare __do_copy_data and __do_clear_bssAyke van Laethem3-2/+18
2022-12-24[NFC][Codegen][AVR] Make shift.ll autogenerate-ableRoman Lebedev1-181/+240
2022-12-23[AVR] Select 16-bit LDS/STS for load/store on AVRTiny.Ben Shi1-7/+17
2022-12-23[AVR][MC] Fix illegal operand forms.Ben Shi2-44/+44
2022-12-23[AVR] Fix a bug in AsmPrinter when printing memory operands.Ben Shi1-0/+88
2022-12-22[AVR] Do not emit instructions invalid for attiny10Ayke van Laethem7-95/+304
2022-11-28[AVR] Do not use R0/R1 on avrtinyAyke van Laethem4-19/+192
2022-11-27[AVR] Remove unused register scavengerAyke van Laethem2-12/+44
2022-11-23[AVR] Fix wrong ABI of AVRTiny.Ben Shi1-68/+280
2022-08-15[AVR] Only push and clear R1 in interrupts when necessaryAyke van Laethem4-21/+123
2022-08-15[AVR] Use @earlyclobber instead of register scavengingAyke van Laethem1-30/+0
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