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path: root/llvm/test/CodeGen/AMDGPU/valu-i1.ll
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2024-01-16[AMDGPU,test] Change llc -march= to -mtriple= (#75982)Fangrui Song1-1/+1
2022-12-01AMDGPU: Convert some assorted tests to opaque pointersMatt Arsenault1-32/+32
2022-07-21[AMDGPU] Combine s_or_saveexec, s_xor instructions.Thomas Symalla1-6/+2
2021-11-20[AMDGPU] Do not generate ELF symbols for the local branch target labelsRamNalamothu1-12/+12
2021-04-06[AMDGPU] Fix typo in regular expression checks. NFC.Jay Foad1-1/+1
2021-01-02[AMDGPU][SimplifyCFG] Teach AMDGPUUnifyDivergentExitNodes to preserve {,Post}...Roman Lebedev1-1/+1
2021-01-02[NFC][CodeGen][Tests] Mark all tests that fail to preserve DomTree for Simpli...Roman Lebedev1-1/+1
2020-04-06[AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.Konstantin Pyzhov1-2/+2
2020-04-06Revert e1730cfeb3588f20dcf4a96b181ad52761666e52Konstantin Pyzhov1-2/+2
2020-04-06[AMDGPU] Disable 'Skip Uniform Regions' optimization by default for AMDGPU.Konstantin Pyzhov1-2/+2
2020-01-22[AMDGPU] SIRemoveShortExecBranches should not remove branches exiting loopsCarl Ritson1-1/+2
2020-01-22Resubmit: [AMDGPU] Invert the handling of skip insertion.cdevadas1-25/+17
2020-01-21Revert "[AMDGPU] Invert the handling of skip insertion."Nicolai Hähnle1-17/+25
2020-01-15[AMDGPU] Invert the handling of skip insertion.cdevadas1-25/+17
2019-11-26[AMDGPU] Fix emitIfBreak CF lowering: use temp reg to make register coalescer...vpykhtin1-3/+2
2019-10-14[AMDGPU] Come back patch for the 'Assign register class for cross block value...Alexander Timofeev1-3/+3
2019-06-14[MBP] Move a latch block with conditional exit and multi predecessors to top ...Guozhi Wei1-1/+1
2019-06-06[AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fddAlexander Timofeev1-3/+3
2019-05-26 [AMDGPU] Divergence driven ISel. Assign register class for cross block va...Alexander Timofeev1-3/+3
2019-05-25Revert r361644, "[AMDGPU] Divergence driven ISel. Assign register class for c...Peter Collingbourne1-3/+3
2019-05-24[AMDGPU] Divergence driven ISel. Assign register class for cross block values...Alexander Timofeev1-3/+3
2019-04-17AMDGPU: Force skip over SMRD, VMEM and s_waitcnt instructionsRhys Perry1-0/+3
2019-02-22[LowerSwitch][AMDGPU] Do not handle impossible valuesRoman Tereshin1-4/+4
2018-10-31AMDGPU: Rewrite SILowerI1Copies to always stay on SALUNicolai Haehnle1-9/+9
2018-10-31AMDGPU: Remove PHI loop condition optimizationNicolai Haehnle1-7/+3
2018-09-11[AMDGPU] Preliminary patch for divergence driven instruction selection. Immed...Alexander Timofeev1-0/+1
2018-08-02[AMDGPU] Avoid using divergent value in mubuf addr64 descriptorTim Renouf1-2/+1
2018-06-29AMDGPU: Don't use struct type for argument layoutMatt Arsenault1-1/+1
2018-06-26AMDGPU: Add pass to lower kernel arguments to loadsMatt Arsenault1-1/+1
2018-05-25[AMDGPU] Fixed incorrect break from loopTim Renouf1-1/+3
2018-04-25[AMDGPU] Revert b0efc4fd6 (https://reviews.llvm.org/D40556)Alexander Timofeev1-2/+2
2017-12-04[CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih1-1/+1
2017-12-01[AMDGPU] SiFixSGPRCopies should not modify non-divergent PHIAlexander Timofeev1-2/+2
2017-08-16[AMDGPU] Eliminate no effect instructions before s_endpgmStanislav Mekhanoshin1-6/+0
2017-07-26[AMDGPU] Optimize SI_IF lowering for simple if regionsStanislav Mekhanoshin1-9/+6
2017-06-02[AMDGPU] Turn on the new waitcnt insertion pass. Adjust tests.Mark Searles1-6/+2
2017-04-12AMDGPU : Fix common dominator of two incoming blocks terminates with uniform ...Wei Ding1-2/+2
2017-03-24AMDGPU: Unify divergent function exits.Matt Arsenault1-6/+77
2017-03-21AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernelMatt Arsenault1-4/+4
2017-03-11[AMDGPU] Remove getBidirectionalReasonRankStanislav Mekhanoshin1-1/+1
2016-11-29AMDGPU/SI: Avoid moving PHIs to VALU when phi values are defined in scalar br...Tom Stellard1-3/+2
2016-11-22[AMDGPU] Fix multiple vreg definitions in si-lower-control-flowStanislav Mekhanoshin1-7/+7
2016-09-30AMDGPU: Use unsigned compare for eq/neMatt Arsenault1-5/+5
2016-08-22AMDGPU: Split SILowerControlFlow into two piecesMatt Arsenault1-9/+32
2016-08-10AMDGPU: Change insertion point of si_mask_branchMatt Arsenault1-5/+5
2016-05-21AMDGPU: Handle cbranch vccz/vccnzMatt Arsenault1-2/+1
2016-05-21AMDGPU: Implement AnalyzeBranchMatt Arsenault1-14/+13
2016-04-29RegisterPressure: Fix default lanemask for missing regunit intervalsMatthias Braun1-1/+1
2016-03-28CodeGen: Correct specification of PHI nodesMatthias Braun1-2/+2
2016-02-12AMDGPU/SI: Detect uniform branches and emit s_cbranch instructionsTom Stellard1-6/+9
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