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path: root/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
AgeCommit message (Expand)AuthorFilesLines
2024-04-16[AMDGPU] Stop reserving $vcc_hi in wave32 mode (#87783)Jay Foad1-11/+11
2024-01-18[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)Jay Foad1-79/+79
2024-01-17[AMDGPU] CodeGen for GFX12 8/16-bit SMEM loads (#77633)Jay Foad1-12/+12
2024-01-16[AMDGPU,test] Change llc -march= to -mtriple= (#75982)Fangrui Song1-2/+2
2023-12-15[AMDGPU] CodeGen for SMEM instructions (#75579)Mirko Brkušanin1-0/+1329
2023-10-27[AMDGPU] make v32i16/v32f16 legal (#70484)Changpeng Fang1-250/+254
2023-10-09Revert "[CodeGen] Really renumber slot indexes before register allocation (#6...Jay Foad1-1170/+1185
2023-10-09[CodeGen] Really renumber slot indexes before register allocation (#67038)Jay Foad1-1185/+1170
2023-09-19[CodeGen] Renumber slot indexes before register allocation (#66334)Jay Foad1-333/+333
2023-09-11[test] Change llc -march= to -mtriple=Fangrui Song1-2/+2
2023-07-07[AMDGPU] Implement whole wave register spillChristudasan Devadasan1-178/+179
2023-06-17[AMDGPU] Generate checks for load-constant testsJay Foad1-937/+1364
2023-03-12Reland rGf35a09daebd0a90daa536432e62a2476f708150d and rG63854f91d3ee1056796a5...Chen Zheng1-48/+32
2023-03-12[DAG] visitAND - fold (and (any_ext V), c) -> (zero_ext (and (trunc V), c)) i...Simon Pilgrim1-48/+48
2023-03-03[AMDGPU] Vectorize misaligned global loads & storesJeffrey Byrnes1-4/+4
2023-02-13Revert "[DAGCombiner] handle more store value forwarding"Arthur Eubanks1-32/+48
2023-02-01[DAGCombiner] handle more store value forwardingChen Zheng1-48/+32
2023-01-23AMDGPU: Clean up LDS-related occupancy calculationsNicolai Hähnle1-892/+892
2022-12-21Revert "[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRs"Christudasan Devadasan1-148/+148
2022-12-19[AMDGPU] Convert some tests to opaque pointers (NFC)Nikita Popov1-123/+123
2022-12-17[AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRsChristudasan Devadasan1-148/+148
2022-09-15AMDGPU: Use GlobalPriority for largest register tuplesMatt Arsenault1-730/+732
2022-09-12CodeGen: Set MODereferenceable from isDereferenceableAndAlignedPointerMatt Arsenault1-10/+7
2022-07-27[AMDGPU] Aggressively schedule to reduce RP in occupancy limited regionsAustin Kerbow1-235/+237
2022-06-30[AMDGPU] Make v16i16/v16f16 legalPiotr Sobczak1-376/+359
2022-05-18[AMDGPU] Aggressively fold immediates in SIFoldOperandsJay Foad1-1065/+998
2022-01-24[AMDGPU] Make v8i16/v8f16 legalStanislav Mekhanoshin1-4/+4
2021-12-01[AMDGPU] Set most sched model resource's BufferSize to oneAustin Kerbow1-944/+921
2021-09-14RegAllocGreedy: Account for reserved registers in num regs heuristicMatt Arsenault1-1120/+1123
2021-09-14[AMDGPU] Switch PostRA sched to MachineSchedJoe Nash1-230/+242
2021-08-10AMDGPU: Add alloc priority to global rangesMatt Arsenault1-865/+882
2021-01-26[AMDGPU] Update subtarget features for new target ID supportAustin Kerbow1-96/+96
2021-01-06[NFC] Removed unused prefixes from CodeGen/AMDGPUMircea Trofin1-4/+4
2020-11-03[DAG] computeKnownBits - Move (most) ISD::SRL handling into KnownBits::lshrSimon Pilgrim1-262/+254
2020-11-03[AMDGPU] Regenerate load i16 tests to use update_llc_test_checks.py script. N...Simon Pilgrim1-324/+7021
2019-03-27[LegalizeVectorTypes] Allow single loads and stores for more short vectorsJustin Bogner1-14/+12
2018-03-29AMDGPU: Fix selection error on constant loads with < 4 byte alignmentMatt Arsenault1-0/+12
2018-02-13[AMDGPU] Change constant addr space to 4Yaxun Liu1-80/+80
2017-05-23[AMDGPU] Add INDIRECT_BASE_ADDR to R600_Reg32 class (PR33045)Simon Pilgrim1-1/+1
2017-03-21AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernelMatt Arsenault1-40/+40
2017-01-24Enable FeatureFlatForGlobal on Volcanic IslandsMatt Arsenault1-1/+1
2017-01-06AMDGPU/R600: Don't use REGISTER_{LOAD,STORE} ISD nodesJan Vesely1-60/+78
2016-11-10AMDGPU: Add VI i16 supportTom Stellard1-4/+11
2016-11-04Revert "AMDGPU: Add VI i16 support"Tom Stellard1-11/+4
2016-11-03AMDGPU: Add VI i16 supportTom Stellard1-4/+11
2016-09-08[SelectionDAG] Add BUILD_VECTOR support to computeKnownBits and SimplifyDeman...Simon Pilgrim1-3/+4
2016-09-06[AMDGPU] Wave and register controlsKonstantin Zhuravlyov1-1/+1
2016-08-29AMDGPU/SI: Implement a custom MachineSchedStrategyTom Stellard1-2/+2
2016-08-27AMDGPU/R600: Enable Load combineJan Vesely1-26/+183
2016-07-01AMDGPU: Improve load/store of illegal types.Matt Arsenault1-353/+33
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