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2024-04-04[CostModel][X86] Add costkinds test coverage for masked load/store/gather/sca...Simon Pilgrim5-16/+7255
2024-04-04[CostModel][X86] Update AVX1 sext v4i1 -> v4i64 cost based off worst case llv...Simon Pilgrim2-3/+3
2024-04-04[CostModel][X86] Update AVX1 sext v8i1 -> v8i32 cost based off worst case llv...Simon Pilgrim2-5/+5
2024-04-04[RISCV][TTI] Scale the cost of intrinsic stepvector with LMUL (#87301)Shih-Po Hung1-89/+54
2024-04-02[FPEnv][CostModel] Correct strictfp test.Kevin P. Neal2-2/+2
2024-04-02[RISCV][TTI] Scale the cost of trunc/fptrunc/fpext with LMUL (#87101)Shih-Po Hung4-276/+276
2024-04-02[RISCV][TTI] Scale the cost of intrinsic umin/umax/smin/smax with LMUL (#87245)Shih-Po Hung1-60/+60
2024-04-01Recommit "[RISCV] Refine cost on Min/Max reduction (#79402)" (#86480)Shih-Po Hung4-230/+230
2024-03-31[memoryssa] Exclude llvm.allow.{runtime,ubsan}.check() (#86066)Vitaly Buka1-0/+29
2024-03-31[Analysis] Exclude llvm.allow.{runtime,ubsan}.check() from AliasSetTracker (#...Vitaly Buka1-0/+30
2024-03-31[CostModel] No cost for llvm.allow.{runtime,ubsan}.check() (#86064)Vitaly Buka2-0/+12
2024-03-26Recommit "[RISCV][TTI] Scale the cost of the sext/zext with LMUL (#86617)"ShihPo Hung5-551/+551
2024-03-26Revert "[RISCV][TTI] Scale the cost of the sext/zext with LMUL (#86617)"ShihPo Hung5-551/+551
2024-03-27[RISCV][TTI] Scale the cost of the sext/zext with LMUL (#86617)Shih-Po Hung5-551/+551
2024-03-25AMDGPU: Rename intrinsics and remove f16/bf16 versions for load transpose (#8...Changpeng Fang1-57/+13
2024-03-25[RISCV][CostModel] Estimate cost of llvm.vector.reduce.fmaximum/fminimum (#80...Shih-Po Hung2-52/+91
2024-03-20[Analysis] Use implicit-check-not in testVitaly Buka1-3/+1
2024-03-20[ValueTracking] Handle range attributes (#85143)Andreas Jonson1-0/+147
2024-03-19[ValueTracking] Handle vector range metadata in isKnownNonZero()Nikita Popov1-4/+1
2024-03-19[ValueTracking] Test isKnownNonZero() range metadata with vector (NFC)Nikita Popov1-0/+14
2024-03-13[RISCV] Add cost model coverage for fixed vector insert with known VLENPhilip Reames1-0/+66
2024-03-13[ValueTracking] Use select condition to help infer bits of armsNoah Goldstein1-4/+4
2024-03-13[ValueTracking] Add tests for inferring select arm bits from condition; NFCNoah Goldstein1-0/+81
2024-03-13[ValueTracking] Remove faulty dereference of "InsertBefore" (#85034)mikaelholmen1-0/+22
2024-03-12[LAA] Fix typo IndidrectUnsafe -> IndirectUnsafe.Florian Hahn2-3/+3
2024-03-12[ValueTracking] Treat phi as underlying obj when not decomposing further (#84...Florian Hahn1-1/+6
2024-03-11[KnownBits] Implement knownbits `lshr`/`ashr` with exact flagNoah Goldstein1-6/+2
2024-03-11[KnownBits] Add test for computing more information for `lshr`/`ashr` with `e...Noah Goldstein1-0/+24
2024-03-11[SystemZ] Provide improved cost estimates (#83873)Dominik Steenken1-0/+128
2024-03-07[LAA] Add test case for #82665.Florian Hahn1-0/+175
2024-03-07[CostModel] getInstructionCost - improve estimation of costs for length chang...Simon Pilgrim11-506/+726
2024-03-06[SCEV] Match both (-1)b + a and a + (-1)b as a - b (#84247)Philip Reames1-1/+1
2024-03-06[SCEV] Precommit test for widened signed induction variablesPhilip Reames1-0/+71
2024-03-06[SCEV] Extend type hint in analysis output to all backedge kindsPhilip Reames54-297/+297
2024-03-06[SCEV] Autogenerate more scev analysis check testsPhilip Reames8-26/+107
2024-03-06[SCEV] Print predicate backedge count only if new information availablePhilip Reames95-1090/+0
2024-03-06[SCEV] Include type when printing constant max backedge taken countPhilip Reames88-491/+491
2024-03-05[SCEV] Migrate a couple tests to be auto generatedPhilip Reames2-71/+221
2024-03-05[SCEV] Migrate some tests to be autogeneratedPhilip Reames14-149/+434
2024-03-05[CostModel][X86] Add test coverage for 'concat subvector' style shufflesSimon Pilgrim4-0/+764
2024-03-04[Analysis] Unify most of the tracking between AssumptionCache and DomConditio...Noah Goldstein1-1/+1
2024-03-04[AArch64] Improve cost model for legal subvec insert/extract (#81135)Graham Hunter1-4/+32
2024-03-04[PowerPC] adjust cost for extract i64 from vector on P9 and above (#82963)Chen Zheng2-4/+4
2024-03-03[AArch64] Add more complete support for BF16David Majnemer1-4/+4
2024-03-02[RISCV] Fix crash when unrolling loop containing vector instructions (#83384)Shih-Po Hung1-0/+53
2024-02-29[RISCV][CostModel] Updates reduction and shuffle cost (#77342)Shih-Po Hung3-26/+26
2024-02-27[LLVM][test] Convert remaining instances of ConstantExpr based splats to use ...Paul Walker1-14/+14
2024-02-23[ValueTracking] Handle more integer intrinsics in `propagatesPoison` (#82749)Yingwei Zheng1-2/+2
2024-02-23[AArch64][CostModel] Improve scalar frem cost (#80423)Paschalis Mpeis2-45/+45
2024-02-21[CostModel][X86] Reduce the extra costs for ICMP complex predicates when an o...Simon Pilgrim1-834/+834
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