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2024-01-06[InstCombine] Fold `switch(zext/sext(X))` into `switch(X)` (#76988)Yingwei Zheng1-0/+19
2024-01-05[NFC] Address review feedback from PR #77004 (#77134)Shubham Sandeep Rastogi1-2/+2
2024-01-05Fix file index verifier when there is no file name in the prologue. (#77004)Shubham Sandeep Rastogi1-2/+7
2024-01-05[llvm][NFC] Refactor AutoUpgrader arm/aarch64 (#74145)Nathan Sidwell1-217/+282
2024-01-06[CVP] Improve the value solving of select at use (#76700)Yingwei Zheng1-25/+26
2024-01-06[InstCombine] Canonicalize `switch(X << C)` into `switch(X)` (#77068)Yingwei Zheng1-0/+27
2024-01-05[RISCV] Don't call use_nodbg_operands for physical registers in RISCVOptWInst...Craig Topper1-1/+5
2024-01-05[ELF] Attempt to set the OS when using 'makeTriple()' (#76992)Joseph Huber1-2/+9
2024-01-05[RemoveDIs] Handle DPValues in FastISel (#76952)Orlando Cazalet-Hyams2-135/+192
2024-01-05[DebugInfo] Correctly track metadata slots for DPValues (#76941)Stephen Tozer1-1/+12
2024-01-05[AsmPrinter][Dwarf5][nfc] Remove template from AccelTable class (#76296)Felipe de Azevedo Piovezan1-37/+25
2024-01-05[InstCombine] Canonicalize `switch(C-X)` to `switch(X)` (#77051)Yingwei Zheng1-0/+12
2024-01-05Revert 4d7c5ad58467502fcbc433591edff40d8a4d697d "[NewPM] Update CodeGenPrepar...Simon Pilgrim8-145/+60
2024-01-05[SimplifyLibCalls] Don't try to manually reprocess callsNikita Popov1-19/+1
2024-01-05[X86][MC] Support encoding/decoding for APX variant MUL/IMUL/DIV/IDIV instruc...Shengchen Kan2-65/+251
2024-01-05[InstCombine] Simplify compare abs(X) and X. (#76385)Z5721-0/+51
2024-01-05[ConstraintElim] Decompose shl nsw for signed predicates (#76961)Nikita Popov1-0/+12
2024-01-05[AMDGPU] Implement readcyclecounter for GFX12 (#76965)Jay Foad4-1/+62
2024-01-05[AMDGPU] Add GXF12 8- and 16-bit SMEM loads (#76966)Jay Foad1-0/+18
2024-01-05[AArch64][GlobalISel] Add legalization for G_VECREDUCE_SEQ_FADD. (#76238)David Green2-0/+37
2024-01-05[X86]Support lowering for APX Promoted SHA/MOVDIR/CRC32/INVPCID/CET instructi...XinWang103-45/+45
2024-01-05[X86][BF16] Try to use `f16` for lowering (#76901)Phoebe Wang3-49/+9
2024-01-05Port CodeGenPrepare to new pass manager (and BasicBlockSectionsProfil… (#75...Nick Anderson8-60/+145
2024-01-05[InstCombine] Revert the `signed icmp -> unsigned icmp` canonicalization when...Yingwei Zheng1-2/+10
2024-01-04[RISCV] Remove isGPRF64AsFPR and isGPRPF64AsFPR functions from AsmParser. NFCCraig Topper2-4/+2
2024-01-05[LoongArch] Fix -Wunused-variable in LoongArchExpandPseudoInsts.cpp (NFC)Jie Fu1-2/+1
2024-01-04X86: add some missing lowerings for shuffles on `bf16` element type. (#76076)Benoit Jacob1-2/+9
2024-01-04[SPIR-V] Emit SPIR-V bitcasts between source/expected pointer type (#69621)Michal Paszkowski3-6/+150
2024-01-05[LoongArch] Reimplement the expansion of PseudoLA*_LARGE instructions (#76555)wanglei4-263/+367
2024-01-05[LoongArch] Emit function call code sequence as `PCADDU18I+JIRL` in medium co...wanglei11-22/+113
2024-01-05DAG: Implement promotion for strict_fp_round (#74332)Matt Arsenault4-3/+69
2024-01-05AMDGPU: Make v4bf16 a legal type (#76217)Matt Arsenault3-18/+39
2024-01-04[InstrProf] No linkage prefixes in IRPGO names (#76994)Ellis Hoag1-19/+8
2024-01-04[dsymutil] Add support for inline DWARF source files. (#77016)Adrian Prantl2-5/+14
2024-01-04[VPlan] Introduce ComputeReductionResult VPInstruction opcode. (#70253)Florian Hahn5-230/+225
2024-01-04[ASAN][AMDGPU] Make address sanitizer checks more efficient for the divergent...Valery Pykhtin1-1/+37
2024-01-04[ORC] Refactor executor symbol lookup to use ExecutorSymbolDef (NFC) (#76989)Ben Langmuir6-14/+20
2024-01-04[RISCV][llvm-mca] Use correct LMUL and SEW for strided loads and stores (#76869)Michael Maitland1-9/+24
2024-01-04[VPlan] Don't replace scalarizing recipe with VPWidenCastRecipe.Florian Hahn1-9/+14
2024-01-04[AArch64] Correct features for Arm Cortex-A78C, Cortex-X1C and Cortex-X2 (#76...Jonathan Thackray1-1/+1
2024-01-04[BasicAA] Guess reasonable contexts for separate storage hints (#76770)David Goldblatt2-8/+29
2024-01-04[RISCV] Remove incomplete PRE_DEC/POST_DEC code for XTHeadMemIdx. (#76922)Craig Topper3-18/+10
2024-01-04[X86] SimplifyDemandedVectorEltsForTargetNode - add X86ISD::VZEXT_LOAD handling.Simon Pilgrim1-0/+14
2024-01-04[llvm-cxxfilt] Added the option --no-params (#75348)Dmitry Vasilyev2-4/+5
2024-01-04[InstCombine] Dont throw away noalias/alias scope metadata when inlining memc...Gabriel Baraldi1-9/+7
2024-01-04AMDGPU: Make bf16/v2bf16 legal types (#76215)Matt Arsenault7-38/+193
2024-01-04[SLP]Use revectorized value for extracts from buildvector, beeingAlexey Bataev1-2/+4
2024-01-04[AMDGPU] Add dynamic LDS size implicit kernel argument to CO-v5 (#65273)Chaitanya5-10/+48
2024-01-04[ConstraintElim] Add debug output for failed preconditionsNikita Popov1-5/+13
2024-01-04[RISCV][CostModel] Add getRISCVInstructionCost() to TTI for CostKind (#76793)Shih-Po Hung4-16/+116
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