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2024-02-21[TargetLowering] Correctly yield NaN from FP_TO_BF16David Majnemer1-5/+4
2024-02-21[VPlan] Do not add call results with void type to State (NFC).Florian Hahn1-1/+2
2024-02-21[NVPTX] Correctly guard int -> bf16 on PTX version and SM versionDavid Majnemer2-10/+12
2024-02-21[VPlan] Support live-ins without underlying IR in type analysis. (#80723)Florian Hahn5-16/+30
2024-02-21[TargetLowering] Actually add the adjustment to the significandDavid Majnemer1-4/+7
2024-02-21[NVPTX] Simplify handling of ISD::BF16_TO_FPDavid Majnemer1-4/+1
2024-02-21[NVPTX] Set ISD::FP_{EXTEND,ROUND} to Custom for more typesDavid Majnemer1-2/+4
2024-02-21[ARM,MC] Support FDPIC relocationsFangrui Song9-10/+76
2024-02-21[AMDGPU] fixes mistake in #82018 (#82223)Nick Anderson1-1/+1
2024-02-21[coro] [async] Don't fail on targets that don't support tail callsMogball1-3/+1
2024-02-21Correctly round FP -> BF16 when SDAG expands such nodes (#82399)David Majnemer5-9/+215
2024-02-21[OpenMP] Remove `register_requires` global constructor (#80460)Joseph Huber1-29/+11
2024-02-21Module::getOrInsertFunction: set debug info format (#82505)Harald van Dijk1-2/+1
2024-02-21Revert "[Coro] [async] Disable inlining in async coroutine splitting (#80904)"Mogball1-34/+47
2024-02-21[LLVM][DWARF] Refactor code for generating DWARF V5 .debug_names (#82394)cmtice1-12/+2
2024-02-21[CostModel][X86] Reduce the extra costs for ICMP complex predicates when an o...Simon Pilgrim1-4/+9
2024-02-21[Offload] Fix NVPTX global entry namesJoseph Huber1-1/+1
2024-02-21[RISCV][TTI] Cost a subvector extract at a register boundary with exact vlen ...Philip Reames1-0/+16
2024-02-21[SystemZ] Use VT (not ArgVT) for SlotVT in LowerCall(). (#82475)Jonas Paulsson1-1/+1
2024-02-21[AArch64][SVE2] Enable dynamic shuffle for fixed length types. (#72490)Dinar Temirbulatov1-11/+49
2024-02-21[CostModel][X86] Fix expanded CTPOP i8 costsSimon Pilgrim1-1/+1
2024-02-21[AArch64] Fix stack probing clobbering flags (#81879)Momchil Velikov1-0/+6
2024-02-21Fix MSVC "not all control paths return a value" warningSimon Pilgrim1-0/+1
2024-02-21Fix MSVC signed/unsigned mismatch warningSimon Pilgrim1-1/+1
2024-02-21[X86] LowerCTPOP - add i3 and i4 LUT 'shift+mask' expansionsSimon Pilgrim1-0/+32
2024-02-21[X86] LowerCTPOP - "ctpop(i2 x) --> sub(x, (x >> 1))"Simon Pilgrim1-0/+12
2024-02-21[AArch64][GlobalISel] Refactor BITCAST Legalization (#80505)chuongg32-6/+63
2024-02-21[LoongArch] Assume no-op addrspacecasts by default (#82332)hev1-0/+5
2024-02-21[RISCV][ISel] Combine vector fadd/fsub/fmul with fp extend. (#81248)Chia1-178/+208
2024-02-21[LLVM][SelectionDAG] Reduce number of ComputeValueVTs variants. (#75614)Paul Walker3-47/+10
2024-02-21[SimplifyIndVar] LCSSA form is destroyed by simplifyLoopIVs, preserve it (#78...Vedant Paranjape1-0/+12
2024-02-21[AMDGPU][TableGen][NFC] Combine predicates without using classes. (#82346)Ivan Kosarev1-10/+4
2024-02-21[AArch64] Fix syntax of gcsstr and gcssttr instructions (#82385)John Brawn1-1/+1
2024-02-21[LIR][SCEVExpander] Restore original flags when aborting transform (#82362)Nikita Popov1-0/+42
2024-02-21[RISCV][SDAG] Fold `select c, ~x, x` into `xor -c, x` (#82462)Yingwei Zheng1-0/+10
2024-02-21[InstCombine] Fold dependent IVs (#81151)Nikita Popov1-0/+55
2024-02-21[RISCV] Fix scheduling info for compressed LD/ST of FP types. (#82339)Francesco Petrogalli1-8/+8
2024-02-21[RISCV] Use TImmLeaf for csr_sysreg (#82463)Wang Pengcheng3-6/+7
2024-02-21[GlobalISel] Clamp out-of-range G_EXTRACT_VECTOR_ELT constant indices when co...Owen Anderson1-7/+11
2024-02-21Revert "Implement convergence control in MIR using SelectionDAG (#71785)"Sameer Sahasrabuddhe17-344/+23
2024-02-21[RISCV] Support llvm.readsteadycounter intrinsicWang Pengcheng3-42/+69
2024-02-20[X86] Add missing pass initialization calls. (#82447)Craig Topper1-0/+2
2024-02-21[AMDGPU] Fix linking error of SIISelLowering.cpp.o (NFC)Jie Fu1-2/+4
2024-02-21Implement convergence control in MIR using SelectionDAG (#71785)Sameer Sahasrabuddhe17-23/+342
2024-02-20[SPIR-V] Fix vloadn OpenCL builtin lowering (#81148)Michal Paszkowski3-19/+26
2024-02-20[GlobalISel] Make sure to check for load barriers when merging G_EXTRACT_VECT...Owen Anderson1-0/+12
2024-02-20[RISCV] Add a query for exact VLEN to RISCVSubtarget [nfc]Philip Reames5-13/+19
2024-02-20[AMDGPU] Fix v_dot2_f16_f16/v_dot2_bf16_bf16 operands (#82423)Stanislav Mekhanoshin3-18/+12
2024-02-20AMDGPU: Use HasFP8ConversionInsts appropriately, NFC (#82433)Changpeng Fang3-6/+9
2024-02-20[AMDGPU] Add v2bf16 for opsel immediate folding (#82435)Stanislav Mekhanoshin1-0/+2
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