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34 hoursUsed only one PatFrag to handle the new constrain introduced.users/cdevadas/enable-codegen-for-constrained-sloadsChristudasan Devadasan1-71/+59
10 daysminor code cleanup.Christudasan Devadasan1-3/+3
10 daysused isXNACKEnabled subtarget option in the PatFrag to optimize the selection.Christudasan Devadasan1-83/+70
10 days[AMDGPU] Codegen support for constrained multi-dword sloadsChristudasan Devadasan1-17/+99
2024-07-03code fixup.Christudasan Devadasan1-1/+1
2024-07-03Used byte width and simplified some more code.Christudasan Devadasan1-16/+12
2024-07-03Removed unwanted helper function hasXnackReplay.Christudasan Devadasan1-1/+0
2024-07-03take the alignment into consideration.Christudasan Devadasan1-29/+23
2024-07-03Used hasXnackReplay call to check if xnack feature is enabled.Christudasan Devadasan1-11/+6
2024-07-03[AMDGPU][SILoadStoreOptimizer] Merge constrained sloadsChristudasan Devadasan2-16/+64
2024-07-03handle the pseudo instruction defs inside a multiclass.users/cdevadas/constrained-sload-insnsChristudasan Devadasan1-18/+17
2024-06-20skip _ec ld insn when data size is lesser or equal to 32.Christudasan Devadasan1-9/+9
2024-06-20[AMDGPU] Define constrained multi-dword scalar load instructions.Christudasan Devadasan1-0/+14
2024-06-20[MC] Eliminate two symbol-related hash maps (#95464)aengelke5-70/+71
2024-06-20[X86] Fix indention in X86InstrArithmetic.td, NFCIShengchen Kan1-199/+187
2024-06-20[LLVM] Add InsertPosition union-type to remove overloads of Instruction-creat...Stephen Tozer3-1341/+105
2024-06-20[ARM] CMSE security mitigation on function arguments and returned values (#89...Lucas Duarte Prates2-15/+33
2024-06-20[MachineLICM] Work-around Incomplete RegUnits (#95926)Pierre van Houtryve1-8/+34
2024-06-20[MC] Remove SectionKind from MCSection (#96067)aengelke18-298/+187
2024-06-20[IR] Remove support for shl constant expressions (#96037)Nikita Popov4-89/+4
2024-06-20[LLVM] Extend setModuleFlag interface. (#86031)Daniel Kiss1-0/+9
2024-06-20Reland "[CVP] Check whether the default case is reachable (#79993)" (#96089)Yingwei Zheng1-0/+32
2024-06-20[RISCV] Lower llvm.clear_cache to __riscv_flush_icache for glibc targets (#93...Roger Ferrer Ibáñez2-0/+28
2024-06-20[PowerPC] Make verifier happy after peephole on MMA COPYs (#94321)Kai Luo1-0/+3
2024-06-19[JITLink] Ensure Edges order is deterministicFangrui Song1-1/+2
2024-06-19[Attributor] Stabilize llvm.assume outputFangrui Song1-11/+16
2024-06-19[LowerTypeTests] Use MapVector to stabilize iteration orderFangrui Song1-1/+1
2024-06-19[PowerPC] Remove extraneous ArrayRef (NFC) (#96092)Kazu Hirata1-6/+6
2024-06-19[Support] Add llvm::xxh3_128bits (#95863)Brendan Duke1-34/+528
2024-06-19[VPlan] Introduce isHeaderMask helper (NFCI).Florian Hahn4-4/+65
2024-06-19[DirectX] Add trig intrinsics and link them with DXIL backend (#95968)Farzon Lotfi1-0/+19
2024-06-19[GlobalMerge] Use MapVector to stabilize iteration orderFangrui Song1-1/+2
2024-06-19[InstCombine] Swap out range metadata to range attribute for arm_mve_pred_v2i...Andreas Jonson1-10/+14
2024-06-19[LV] Consider insts feeding interleave group pointers free.Florian Hahn1-11/+19
2024-06-19[SCEV] Use context sensitive reasoning in howFarToZero (#94525)Philip Reames1-4/+14
2024-06-19[SCEVExpander] Recognize urem idiom during expansion (#96005)Philip Reames2-0/+13
2024-06-19[AVR] Let ArrayRef infer the array size (NFC) (#96076)Kazu Hirata1-4/+4
2024-06-19[NFC][SPARC] Fix typos and style mismatchesKoakuma1-1/+1
2024-06-19[GISel][RISCV]Implement indirect parameter passing (#95429)Gábor Spaits2-32/+102
2024-06-19[AMDGPU] Add IsSingle to a few Interp instructions (#95984)Joe Nash1-1/+1
2024-06-19[AMDGPU] Add IsSingle to V_DIV_FMAS* for consistency. (#95983)Joe Nash1-0/+2
2024-06-19[AArch64] Avoid using NEON BSL for streaming[-compatible] functions (#95803)Sander de Smalen1-3/+5
2024-06-19[AArch64] Let patterns for NEON instructions check runtime mode. (#95560)Sander de Smalen4-33/+32
2024-06-19[InstCombine] Preserve all gep flags in gep of exact div foldNikita Popov1-4/+3
2024-06-19[RISCV] Move RISCVInsertVSETVLI::coalesceVSETVLIs back to before insertReadVL...Luke Lau1-5/+5
2024-06-19[InstCombine] Preserve all gep flags when emitting offsetNikita Popov1-1/+1
2024-06-19[InstCombine] Preserve all gep flags in gep of select foldNikita Popov1-3/+3
2024-06-19[InstCombine] Preserve all gep flags in dependent IV foldNikita Popov1-1/+1
2024-06-19[X86] computeKnownBitsForPMADDWD/PMADDUBSW - tidyup line overflow by moving e...Simon Pilgrim1-21/+13
2024-06-19[InstCombine] Preserve all gep flags in another select of gep foldNikita Popov1-3/+2
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