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2024-04-16[𝘀𝗽𝗿] initial versionWang Pengcheng3-26/+18
2024-04-16[RISCV] Add scheduling information for SiFive VCIX (#86093)Michal Terepeta9-12/+149
2024-04-15[RISCV] Change how MMO is rebuilt in lowerFixedLengthVectorLoadToRVV/lowerFix...Craig Topper1-14/+5
2024-04-15[RISCV] Correct the spelling of the Zcmop mnemonics. (#88826)Craig Topper1-1/+1
2024-04-15[RISCV] Remove unnecessary NoHasStdExtZicfiss Predicate from cmop.1 and cmop....Craig Topper1-7/+1
2024-04-15[RISCV] Add FeatureStdExtI to all CPUs in RISCVProcessors.td. NFC (#88805)Craig Topper1-2/+25
2024-04-16Revert "[X86] Remove obsolete tablegen rules for near data in small static co...Arthur Eubanks1-0/+22
2024-04-15[X86] Remove obsolete tablegen rules for near data in small static code model...Arthur Eubanks1-22/+0
2024-04-15[RISCV] Provide a more efficient lowering for experimental.cttz.elts. (#88552)Craig Topper2-0/+38
2024-04-16[RISCV][TTI] Scale the cost of ICmp with LMUL (#88235)Shih-Po Hung1-8/+9
2024-04-16[InterleavedAccessPass] Get round the unsupported large scalarize vectors (#8...Allen1-1/+1
2024-04-15[RISCV] Expand mul to shNadd x, (slli x, c) in DAGCombine (#88524)Philip Reames1-3/+49
2024-04-15[NFC] Refactor looping over recomputeLiveIns into function (#88040)Kai Nacke7-55/+12
2024-04-15[RISCV] Add missing space to RISCVInstrInfoZvk.td. NFCCraig Topper1-1/+1
2024-04-16[RISCV] Fix assertion failure in `genShXAddAddShift` (#88757)Yingwei Zheng1-1/+1
2024-04-15Resolve static analyser report on pointer dereferencing after null check (#88...mmoadeli1-18/+15
2024-04-15[SystemZ] Bugfix in getDemandedSrcElements(). (#88623)Jonas Paulsson1-1/+1
2024-04-15[AArch64][SME] Create new pass to remove COALESCER_BARRIER early. (#85386)Sander de Smalen4-0/+111
2024-04-15[HLSL][SPIRV] Add any intrinsic lowering (#88325)Farzon Lotfi1-4/+25
2024-04-15[RISCV] Split PseudoVFMIN, PseudoVFMAX PseudoVFSGNJ, PseudoVFSGNJN, and Pseud...Michael Maitland6-62/+79
2024-04-15[RISCV] Split narrowing convert to FP pseudos by SEWMichael Maitland6-55/+78
2024-04-15[RISCV] Split Widening convert to FP pseudos by SEWMichael Maitland7-71/+168
2024-04-15[RISCV] Split single width convert to FP pseudos by SEWMichael Maitland6-54/+51
2024-04-15[LLVM][SelectionDAG] Allow verification of target ISD nodes. (#88121)Paul Walker2-0/+47
2024-04-15[X86] Remove scaleVectorShuffleBlendMask and use APIntOps::ScaleBitMask direc...Simon Pilgrim1-13/+5
2024-04-15[LLVM][CodeGen][AArch64] Remove bogus lowering of sve_while{gt/ge/hi/hs} intr...Paul Walker1-27/+12
2024-04-15[LLVM][SVE][CodeGen] Fix incorrect isel for signed saturating instructions. (...Paul Walker3-2/+87
2024-04-15[X86] Remove unused function (NFC)Jie Fu1-8/+0
2024-04-15[X86] Add isCompletePermute helper for single input shuffles where we don't l...Simon Pilgrim1-16/+18
2024-04-15[LoongArch] Fix incorrect logic in isLegalAddressingMode() (#88694)wanglei1-8/+7
2024-04-15[ARM][Thumb2] Mark BTI-clearing instructions as scheduling region boundaries ...Victor Campos2-0/+23
2024-04-15Support for i8/i16 for bitreverse using GFNI. (#88625)shamithoke1-5/+9
2024-04-15[AArch64][GlobalISel] Extend scalar lrint legalization. (#88360)David Green2-17/+4
2024-04-15[SPIR-V] Update type inference and instruction selection (#88254)Vyacheslav Levytskyy15-38/+267
2024-04-15[ARM] Don't include IRBuilder.h in ARMISelLowering.h (NFC)Nikita Popov2-1/+2
2024-04-15[CodeGen] Let `CodeGenPassBuilder` know concrete target machine (#88614)paperchalice1-2/+3
2024-04-15[LoongArch] Return true from shouldConsiderGEPOffsetSplit (#88371)wanglei1-0/+1
2024-04-14[AArch64] Improve cost of non-zero lane splatsDavid Green1-1/+4
2024-04-13[X86][BF16] Improve vectorization of BF16 (#88486)Phoebe Wang1-24/+29
2024-04-13AMDGPU: Undo atomicrmw add/sub/xor 0 -> atomicrmw or canonicalization (#87533)Matt Arsenault1-2/+25
2024-04-12[SystemZ] Add custom handling of legal vectors with reduce-add. (#88495)Dominik Steenken4-5/+72
2024-04-12[RISCV] Remove mayLoad = 1 from store-conditional (#88470)Francis Visoiu Mistrih1-2/+15
2024-04-12[RISCV] Support uimm32 immediates in RISCVInstrInfo::movImm for RV32. (#88464)Craig Topper1-2/+9
2024-04-12[RISCV] Split PseudoVFRSQRT7 and PseudoVFREC7 by SEWMichael Maitland4-33/+52
2024-04-12[RISCV] Split widening floating point fused multiple-add pseudo instructions ...Michael Maitland7-69/+70
2024-04-12[RISCV] Split single width floating point fused multiple-add pseudo instructi...Michael Maitland7-150/+246
2024-04-12[RISCV] Split PseudoVFMUL by SEWMichael Maitland6-24/+26
2024-04-12[RISCV] Split PseudoVFWADD, PseudoVFWSUB, and PseudoVFWMUL by SEWMichael Maitland7-111/+203
2024-04-12[RISCV] Split PseudoVFADD, PseudoVFSUB, and PseudoVFRSUB by SEWMichael Maitland6-34/+52
2024-04-12[AMDGPU] Fix a potential wrong return value indicating whether a pass modifie...Shilei Tian1-1/+1
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