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2024-04-19[X86] LowerFunnelShift - improve handling of vXi8 constant splat funnel shiftsSimon Pilgrim1-1/+24
2024-04-19AMDGPU: Refactor unsafe atomicrmw remark emission (#89379)Matt Arsenault1-15/+18
2024-04-19[SystemZ] Add TPEI instruction and Associated Facility (#89372)Dominik Steenken5-4/+14
2024-04-19[SystemZ] Fix Operand Retrieval for Vector Reduction Intrinsic in `shouldExpa...Dominik Steenken1-14/+11
2024-04-19[SystemZ][z/OS] Implement llvm.frameaddr for XPLINK (#89284)Kai Nacke3-14/+49
2024-04-19[AArch64][SVE2] Generate SVE2 BSL instruction in LLVM for add/sub. (#88413)Dinar Temirbulatov1-2/+2
2024-04-19[AMDGPU] Allow any linkage for dynlds (#84742)Pierre van Houtryve1-7/+3
2024-04-19[AArch64] Remove invalid uabdl patterns. (#89272)David Green1-10/+0
2024-04-19[SPIR-V] SPIR-V Backend must generate a valid OCL version if working in OpenC...Vyacheslav Levytskyy1-3/+14
2024-04-19[X86][APX] Remove KEYLOCKER and SHA promotions from EVEX MAP4. (#89173)Freddy Ye4-92/+33
2024-04-18[RISCV] Remove unused HasStdExtZama16b Predicate. NFCCraig Topper1-3/+0
2024-04-18[AMDGPU][MC] Separate VOPC MnemonicAlias from Instruction (#89105)Joe Nash1-105/+117
2024-04-18 [AMDGPU] Add disassembler diagnostics for invalid kernel descriptors (#87400)Emma Pilkington3-113/+184
2024-04-18[SPIR-V] Fix return type when sampling an image with OpImageSampleExplicitLod...Vyacheslav Levytskyy3-3/+6
2024-04-18[AVR] Let ArrayRef infer the array size (NFC) (#88638)Kazu Hirata1-4/+4
2024-04-18[X86] ptest is commutable as long as only the Z flag is used. (#88969)Craig Topper1-0/+37
2024-04-18[AMDGPU] Support wide register or subregister access when emitting s_singleus...Scott Egerton1-6/+19
2024-04-18[RISCV] Remove IsEABI from RISCVZC::getStackAdjBase. (#89177)Craig Topper3-10/+5
2024-04-18[AMDGPU] Fix end() iterator dereference in SILowerSGPRSpills (#88828)bcahoon1-4/+5
2024-04-18[AMDGPU] Fix debug line table for MSG_DEALLOC_VGPRS optimization (#88924)Emma Pilkington1-2/+3
2024-04-18[AArch64][CodeGen] Fix illegal register aliasing bug for mops instrs (#88869)Nashe Mncube1-1/+1
2024-04-18[AMDGPU][AtomicOptimizer] Fix DT update for divergent values with Iterative s...Pierre van Houtryve1-9/+20
2024-04-18[X86] Use m_APIntAllowPoison instead of m_APIntAllowUndefNikita Popov1-2/+2
2024-04-18[IR][PatternMatch] Only accept poison in getSplatValue() (#89159)Nikita Popov2-4/+21
2024-04-17[RISCV] Remove unused Predicates for I and E extensions. NFCCraig Topper1-5/+1
2024-04-18[RISCV] Use vnclip for scalable vector saturating truncation. (#88648)Chia2-37/+70
2024-04-17[RISCV] Speed up RISCVRegisterInfo::needsFrameBaseReg when frame pointer isn'...Craig Topper1-10/+12
2024-04-18[RISCV] Check that VLMAX is the same when demanding exact VL (#89080)Luke Lau1-1/+1
2024-04-18[PowerPC] `ANDI_rec_1_*` should define CR0 (#89034)Kai Luo1-0/+2
2024-04-18[RISCV][TTI] Refine the cost of FCmp (#88833)Shih-Po Hung1-10/+38
2024-04-17CodeGenPrepare: Add support for llvm.threadlocal.address address-mode sinking...Matthias Braun2-0/+26
2024-04-17AMDGPU: Fix not handling atomicrmw fadd in exotic address spaces correctlyMatt Arsenault1-1/+1
2024-04-17[X86] Always use 64-bit relocations in no-PIC large code model (#89101)Arthur Eubanks1-4/+3
2024-04-17[llvm][NVPTX] Don't emit unused var 'temp_param_reg' (NFC) (#89004)Youngsuk Kim1-2/+1
2024-04-17[AArch64] Update latencies for Cortex-A510 scheduling model (#87293)Usman Nadeem1-70/+75
2024-04-17[CostModel][X86] Recognise vector rotation by uniform constant patternsSimon Pilgrim1-7/+34
2024-04-17[GlobalISel][AArch64] Add LLRINT support (#88702)David Green2-1/+2
2024-04-17[RISCV] Fix typo in RISCVScheduleV.td that was introduced in 60a1158Michael Maitland1-1/+1
2024-04-17[CostModel][X86] Update BITREVERSE costs for GFNI targetsSimon Pilgrim1-17/+24
2024-04-17[AMDGPU] Fix predicates for BUFFER_ATOMIC_FMIN/FMAX patterns (#89066)Jay Foad1-1/+1
2024-04-17[RISCV] Explicitly bail if something modifies VL/VTYPE in doLocalPostpassLuke Lau1-0/+3
2024-04-17[PowerPC] 32-bit large code-model support for toc-data (#85129)Zaara Syeda6-36/+77
2024-04-17[RISCV] Fix clang-tidy warning about else after return. NFCLuke Lau1-1/+3
2024-04-17[RISCV] Assert only valid AVLs in doLocalPostpass are X0 or virtual regs. NFCLuke Lau1-9/+7
2024-04-17[SPIR-V] Account for zext in a llvm intrinsic call (#88903)Vyacheslav Levytskyy1-0/+25
2024-04-17[SPIR-V] Improve Tablegen instruction selection and account for a pointer siz...Vyacheslav Levytskyy9-74/+104
2024-04-17Move gfni for bitreverse check out of SSSE3. (#88938)shamithoke1-7/+7
2024-04-17AMDGPU: Move libcall simplify into PeepholeEP (#88853)Matt Arsenault1-3/+10
2024-04-17[RISCV] Support Zama16b1p0 (#88474)Jesse Huang1-0/+7
2024-04-16[RISCV] Simplify FindRegWithEncoding in copyPhysRegVector. NFC (#89001)Craig Topper1-9/+6
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