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2024-02-23[AMDGPU] Simplify AMDGPUDisassembler::getInstruction by removing Res. (#82775)Jay Foad2-151/+119
2024-02-23[AMDGPU][NFC] Have helpers to deal with encoding fields. (#82772)Ivan Kosarev10-89/+74
2024-02-23[NFC] clean up memtag-stack code (#80906)Florian Mayer1-9/+2
2024-02-23[RISCV][NFC] Allow SchedVar to be a def inside our scheduler model files. (#8...Michael Maitland1-8/+13
2024-02-23[AMDGPU] Fix encoding of VOP3P dpp on GFX11 and GFX12 (#82710)Stanislav Mekhanoshin2-0/+3
2024-02-23[AArch64][CostModel] Improve scalar frem cost (#80423)Paschalis Mpeis1-0/+7
2024-02-23[ARM][GlobalISel] Remove legacy legalizer rules (#82619)Pierre van Houtryve1-47/+9
2024-02-23[RISCV] Add asserts for insert/extract_subvector invariants. NFCLuke Lau1-2/+6
2024-02-23[RISCV][VP] Introduce vp saturating addition/subtraction and RISC-V support. ...Yeting Kuo1-1/+11
2024-02-23[RISCV] Use RISCVSubtarget::getRealVLen() in more places. NFCLuke Lau1-18/+13
2024-02-22[SelectionDAG][RISCV] Use FP type for legality query for LRINT/LLRINT in Lega...Craig Topper1-1/+1
2024-02-22[WebAssembly] Disable multivalue emission temporarily (#82714)Heejin Ahn4-15/+32
2024-02-22[NVPTX] fixup support for unaligned parameters and returns (#82562)Alex MacLean3-20/+271
2024-02-22[RISCV] Vector sub (zext, zext) -> sext (sub (zext, zext)) (#82455)Philip Reames1-1/+24
2024-02-22[AMDGPU][NFC] Refactor SIInsertWaitcnts zero waitcnt generation (#82575)vangthao952-15/+22
2024-02-22[Hexagon] Clean up redundant transfer instructions. (#82663)Sumanth Gundapaneni3-0/+335
2024-02-22[NewPM/CodeGen] Rewrite pass manager nesting (#81068)Arthur Eubanks2-9/+7
2024-02-22[AArch64][CodeGen] Fix crash when fptrunc returns fp16 with +nofp attr (#81724)Nashe Mncube1-5/+9
2024-02-22[DirectX][NFC] Use LLVM Types in DXIL Operation specifications in DXIL.td (#8...S. Bharadwaj Yadavalli1-46/+34
2024-02-22[HEXAGON] Fix bit boundary for isub_hi in HexagonBitSimplify (#82336)yandalur1-1/+2
2024-02-22[RISCV] Enable -riscv-enable-sink-fold by default. (#82026)Craig Topper1-1/+1
2024-02-23[RISCV][SDAG] Improve codegen of select with constants if zicond is available...Yingwei Zheng1-0/+20
2024-02-22[AArch64] Remove unused ReverseCSRRestoreSeq option. (#82326)Sander de Smalen1-45/+21
2024-02-22[AArch64] Mangle names of all ARM64EC functions with entry thunks (#80996)Billy Laws2-2/+3
2024-02-22[AMDGPU] Remove DPP DecoderNamespaces. NFC. (#82491)Jay Foad6-400/+288
2024-02-22[AArch64] Switch to soft promoting half types. (#80576)Harald van Dijk1-0/+2
2024-02-22[AMDGPU] Clean up conversion of DPP instructions in AMDGPUDisassembler (#82480)Jay Foad1-74/+53
2024-02-22Add support for the SPV_INTEL_usm_storage_classes extension (#82247)Vyacheslav Levytskyy11-28/+99
2024-02-22[AArch64] Fix sched model for TSV110 core. (#82343)Yury Gribov1-3/+3
2024-02-22[AMDGPU] Split Dpp8FI and Dpp16FI operands (#82379)Jay Foad8-46/+43
2024-02-22[SPIRV] Prevent creation of jump tables from switch (#82287)Vyacheslav Levytskyy1-0/+3
2024-02-22[SPIRV] Add support for the SPV_KHR_subgroup_rotate extension (#82374)Vyacheslav Levytskyy5-1/+25
2024-02-22[AArch64] Restore Z-registers before P-registers (#79623) (#82492)CarolineConcatto1-9/+10
2024-02-22[AMDGPU][GlobalISel] Add fdiv / sqrt to rsq combine (#78673)Nick Anderson2-1/+30
2024-02-22[RISCV] Compute integers once in isSimpleVIDSequence. NFCI (#82590)Luke Lau1-35/+29
2024-02-22[RISCV] Teach RISCVMakeCompressible handle Zca/Zcf/Zce/Zcd. (#81844)Yeting Kuo2-8/+27
2024-02-22[RISCV] Fix mgather -> riscv.masked.strided.load combine not extending indice...Luke Lau1-8/+12
2024-02-21[Hexagon] Optimize post-increment load and stores in loops. (#82418)Sumanth Gundapaneni6-1/+772
2024-02-21[Hexagon] Generate absolute-set load/store instructions. (#82034)Sumanth Gundapaneni3-0/+284
2024-02-21[NVPTX] Correctly guard int -> bf16 on PTX version and SM versionDavid Majnemer2-10/+12
2024-02-21[NVPTX] Simplify handling of ISD::BF16_TO_FPDavid Majnemer1-4/+1
2024-02-21[NVPTX] Set ISD::FP_{EXTEND,ROUND} to Custom for more typesDavid Majnemer1-2/+4
2024-02-21[ARM,MC] Support FDPIC relocationsFangrui Song4-1/+60
2024-02-21[AMDGPU] fixes mistake in #82018 (#82223)Nick Anderson1-1/+1
2024-02-21Correctly round FP -> BF16 when SDAG expands such nodes (#82399)David Majnemer3-5/+87
2024-02-21[CostModel][X86] Reduce the extra costs for ICMP complex predicates when an o...Simon Pilgrim1-4/+9
2024-02-21[RISCV][TTI] Cost a subvector extract at a register boundary with exact vlen ...Philip Reames1-0/+16
2024-02-21[SystemZ] Use VT (not ArgVT) for SlotVT in LowerCall(). (#82475)Jonas Paulsson1-1/+1
2024-02-21[AArch64][SVE2] Enable dynamic shuffle for fixed length types. (#72490)Dinar Temirbulatov1-11/+49
2024-02-21[CostModel][X86] Fix expanded CTPOP i8 costsSimon Pilgrim1-1/+1
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