| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-04-03 | [AMDGPU] Add a missing COV6 case to getAMDHSACodeObjectVersion() (#87492) | Emma Pilkington | 1 | -0/+2 |
| 2024-04-03 | [AMDGPU][MC] Allow VOP3C dpp src1 to be imm or SGPR (#87418) | Joe Nash | 3 | -61/+2 |
| 2024-04-03 | AMDGPU: Use PseudoInstr to name SIMCInstr for DSDIR and SOPs, NFC (#87537) | Changpeng Fang | 2 | -40/+40 |
| 2024-04-03 | [AMDGPU][MC] Enables sgpr or imm src1 for float VOP3 DPP, but excludi… (#87... | Joe Nash | 4 | -9/+33 |
| 2024-04-03 | [X86] getEffectiveX86CodeModel - take a Triple argument instead of just a Is6... | Simon Pilgrim | 1 | -3/+4 |
| 2024-04-03 | [X86] Haswell/Broadwell/Skylake DPPS folded instructions use an extra port06 ... | Simon Pilgrim | 4 | -8/+16 |
| 2024-04-03 | [AMDGPU] Remove useless aliases for FLAT instructions. NFC. (#87462) | Jay Foad | 1 | -2/+2 |
| 2024-04-03 | [AArch64][GlobalISel] Basic add_sat and sub_sat vector handling. (#80650) | David Green | 1 | -5/+8 |
| 2024-04-03 | [MIPS] Fix the opcode of max.fmt and mina.fmt (#85609) | Cinhi Young | 1 | -4/+4 |
| 2024-04-02 | [RISCV] Slightly simplify RVVArgDispatcher::constructArgInfos. NFC (#87308) | Craig Topper | 1 | -4/+2 |
| 2024-04-02 | AMDGPU: Use PseudoInstr instead of Pseudo Mnemonic for SIMCInstr, NFC (#87420) | Changpeng Fang | 1 | -2/+2 |
| 2024-04-02 | [RISCV][NFC] Delete some unused pseudo multiclasses (#87401) | Michael Maitland | 1 | -26/+0 |
| 2024-04-02 | [CallSiteInfo][NFC] CallSiteInfo -> CallSiteInfo.ArgRegPairs (#86842) | Prabhuk | 4 | -7/+8 |
| 2024-04-02 | [RISCV] Lower (vector_interleave X, undef) to (vzext_vl X). (#87283) | Craig Topper | 1 | -1/+10 |
| 2024-04-02 | [WebAssembly] Allocate MCSymbolWasm data on MCContext (#85866) | Tim Neumann | 6 | -74/+39 |
| 2024-04-02 | [X86] canonicalizeShuffleWithOp - don't fold VPERMI(BINOP(X,Y)) -> BINOP(VPER... | Simon Pilgrim | 1 | -5/+9 |
| 2024-04-02 | [RISCV][GISEL] Legalize G_BITCAST for scalable vectors (#85970) | Michael Maitland | 1 | -0/+6 |
| 2024-04-02 | [RISCV] Fix and refactor Zvk sched classes (#86519) | Michael Maitland | 2 | -41/+22 |
| 2024-04-02 | [AArch64] Update Neoverse V2 FSQRT execution units in schedule model. (#86803) | Rin Dobrescu | 1 | -6/+4 |
| 2024-04-02 | [SPIR-V] Fix validity of atomic instructions (#87051) | Vyacheslav Levytskyy | 3 | -10/+128 |
| 2024-04-02 | [MIPS][CallSiteInfo][NFC] Fill CallSiteInfo only when needed (#86847) | Prabhuk | 1 | -1/+1 |
| 2024-04-02 | [RISCV][TTI] Scale the cost of trunc/fptrunc/fpext with LMUL (#87101) | Shih-Po Hung | 1 | -3/+22 |
| 2024-04-02 | [RISCV][TTI] Scale the cost of intrinsic umin/umax/smin/smax with LMUL (#87245) | Shih-Po Hung | 1 | -2/+20 |
| 2024-04-02 | [PPC][NFC] add an option for GatherAllAliasesMaxDepth (#87071) | Chen Zheng | 1 | -0/+6 |
| 2024-04-02 | [AVR][NFC] Improve format of target description files (#87212) | Ben Shi | 1 | -245/+75 |
| 2024-04-01 | [RISCV] ReadStoreData is read later in the pipeline for SiFive7 (#86454) | Michael Maitland | 1 | -1/+1 |
| 2024-04-01 | Recommit "[RISCV] Refine cost on Min/Max reduction (#79402)" (#86480) | Shih-Po Hung | 1 | -7/+36 |
| 2024-04-01 | [AMDGPU] Use glue for convergence tokens at call-like operations (#86766) | Sameer Sahasrabuddhe | 2 | -25/+17 |
| 2024-04-01 | [BPF] expand cttz, ctlz for i32, i64 (#73668) | Yingchi Long | 1 | -5/+4 |
| 2024-04-01 | [AMDGPU] Expose RTZ version of f16 interpolation for gfx11+ (#86614) | Ruiling, Song | 2 | -1/+11 |
| 2024-03-31 | [AMDGPU] Use directive for kernarg preload header padding (#86004) | Austin Kerbow | 1 | -12/+9 |
| 2024-03-31 | [AMDGPU] Extend MFMA padding option to gfx90a+ (#86768) | Austin Kerbow | 1 | -0/+3 |
| 2024-03-31 | [IR][Object][NFC] Move ARM64EC name mangling helpers to Mangler.h. (#87191) | Jacek Caban | 1 | -1/+1 |
| 2024-03-30 | [M68k][NFC] Refactoring memory operands of different sizes with foreach | Min Hsu | 1 | -65/+51 |
| 2024-03-30 | [RISCV] RISCV vector calling convention (2/2) (#79096) | Brandon Wu | 3 | -71/+222 |
| 2024-03-30 | [AMDGPU] Use AMDGPU::isIntrinsicAlwaysUniform in isSDNodeAlwaysUniform (#87085) | Jay Foad | 1 | -6/+1 |
| 2024-03-29 | [DXIL] Add lowering for `ceil` (#87043) | Helena Kotas | 1 | -0/+3 |
| 2024-03-29 | Reland "[NVPTX] Use .common linkage for common globals" (#86824) | Alex MacLean | 1 | -7/+9 |
| 2024-03-29 | [HLSL][DXIL] HLSL's `round` should follow `roundeven` behavior (#87078) | Farzon Lotfi | 1 | -1/+1 |
| 2024-03-29 | [RISCV] Move VPseudoBinaryNoMask multiclass to RISCVInstrInfoZvk.td and renam... | Craig Topper | 2 | -15/+15 |
| 2024-03-29 | [RISCV] Add missing RISCVMaskedPseudo for TIED pseudos (#86787) | Luke Lau | 1 | -2/+4 |
| 2024-03-29 | [RISCV] Combine (or disjoint ext, ext) -> vwadd (#86929) | Luke Lau | 1 | -6/+20 |
| 2024-03-29 | [X86][MC] Support enc/dec for IMULZU. (#86653) | Freddy Ye | 2 | -0/+40 |
| 2024-03-28 | [RISCV] Extend pattern matches involving shNadd to support disjoint or (#87001) | Philip Reames | 1 | -25/+25 |
| 2024-03-28 | [AArch64][GISEL] Consider fcmp true and fcmp false in cond code selection (#8... | Marc Auberer | 1 | -0/+6 |
| 2024-03-29 | [RISCV] Combine ({s,u}{div,rem} (zext, zext)) -> (zext ({s,u}{div,rem} (zext,... | Luke Lau | 1 | -2/+12 |
| 2024-03-28 | [DXIL] Add lowering for `reversebits` and `trunc` (#86909) | Helena Kotas | 1 | -0/+6 |
| 2024-03-28 | [SystemZ] Fix an unused variable warning | Kazu Hirata | 1 | -0/+1 |
| 2024-03-28 | [X86] Add isLogicOp helper to match ISD::AND/OR/XOR and X86ISD::ANDNP | Simon Pilgrim | 1 | -2/+6 |
| 2024-03-28 | [RISCV] Add add_like PatFrags to reduce number of required patterns [nfc] (#8... | Philip Reames | 2 | -9/+7 |
