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path: root/llvm/lib/Target/X86/X86SchedHaswell.td
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2024-04-04[X86] Haswell/Broadwell - fix (V)ROUND*ri sched behaviours to use 2*Port1Simon Pilgrim1-6/+3
2024-04-03[X86] Haswell/Broadwell/Skylake DPPS folded instructions use an extra port06 ...Simon Pilgrim1-2/+4
2024-03-25[X86] HSW/BDW - vector splat shifts don't use Port5 when loading the shift am...Simon Pilgrim1-2/+4
2023-12-11[X86] Rename VBROADCASTF128/VBROADCASTI128 to VBROADCASTF128rm/VBROADCASTI128...Simon Pilgrim1-2/+2
2023-08-24[TableGen] Rename ResourceCycles and StartAtCycle to clarify semanticsMichael Maitland1-152/+152
2023-08-24Revert "[TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics"Michael Maitland1-152/+152
2023-08-24[TableGen] Rename ResourceCycles and StartAtCycle to clarify semanticsMichael Maitland1-152/+152
2023-08-24Revert "[TableGen] Rename ResourceCycles and StartAtCycle to clarify semantics"Michael Maitland1-152/+152
2023-08-24[TableGen] Rename ResourceCycles and StartAtCycle to clarify semanticsMichael Maitland1-152/+152
2022-12-19[X86] Add default LoadUOps argument to Intel models WriteResPair macroSimon Pilgrim1-2/+2
2022-11-19[X86] Remove unnecessary STC instruction overridesSimon Pilgrim1-2/+1
2022-11-14[X86] Remove unnecessary overrides for CBW/CWDE/CDQE/CMC instructionsSimon Pilgrim1-2/+1
2022-11-11[X86] Split int2double and float2double scheduler classes on Haswell/Broadwel...Simon Pilgrim1-14/+8
2022-11-11[X86] Replace unnecessary CVTPS2DQ folded overrides with better base class defsSimon Pilgrim1-10/+0
2022-11-09[X86] Replace unnecessary CVTPS2PI/CVTPS2DQ overrides with better base class ...Simon Pilgrim1-26/+5
2022-11-09[X86] Replace unnecessary CVTSD2SI/CVTSS2SI overrides with better base class ...Simon Pilgrim1-18/+2
2022-11-08[X86] CVTTSS2SI64rm has the same scheduler def as (V)CVTSS2SI64rmSimon Pilgrim1-12/+2
2022-11-07[X86] Folded MOVDDUPrm has the same sched behaviour as MOVSHDUPrm/MOVSLDUPrm ...Simon Pilgrim1-7/+1
2022-11-06[X86] Schedule scalar movsx/movzx load+extend ops as WriteLoad instead of Wri...Simon Pilgrim1-3/+1
2022-11-05[X86] Replace unnecessary int2float and float2double overrides with better ba...Simon Pilgrim1-38/+13
2022-11-05[X86] Cleanup WriteCvtSD2SS/WriteCvtPD2PS overridesSimon Pilgrim1-14/+8
2022-11-05[X86] Fix override for CVTPD2PS/CVTPD2DQ/CVTTPD2DQ AVX variantsSimon Pilgrim1-3/+3
2022-11-05[X86] Replace unnecessary int2double overrides with a better WriteCvtI2PD defSimon Pilgrim1-19/+7
2022-10-29[X86] Remove the WriteDPPSZ schedule pairSimon Pilgrim1-1/+0
2022-09-16[X86] Add missing (unsupported) zmm vector move classesSimon Pilgrim1-2/+2
2022-02-08[X86] Update register RCL/RCR by 1 and immediate scheduling for Intel CPUsCraig Topper1-3/+17
2022-01-19[X86] Add some missing dependency-breaking zero idiom patterns to scheduler m...Simon Pilgrim1-0/+36
2021-12-27[X86] Add scheduler classes for zmm vector reg-reg move instructionsSimon Pilgrim1-0/+2
2021-12-12[X86][MMX] Remove superfluous 'i' from MMX cvt opnames. NFCI.Simon Pilgrim1-10/+10
2021-12-12[X86][MMX] Remove superfluous 'i' from MMX binop opnames. NFCI.Simon Pilgrim1-6/+6
2021-11-07[X86] Update RET/LRET instruction to use the same naming convention as IRET (...Simon Pilgrim1-2/+2
2021-08-26[X86][MCA] Address the latest issues with MULX reported in PR51495.Andrea Di Biagio1-3/+3
2021-08-25[X86][SchedModel] Fix latency the Hi register write of MULX (PR51495).Andrea Di Biagio1-1/+4
2021-08-22[X86] Try to sync HSW + BDW model class defs to simplify comparisons. NFC.Simon Pilgrim1-19/+34
2021-08-20[X86][SchedModels] Fix missing ReadAdvance for MULX and ADCX/ADOX (PR51494)Andrea Di Biagio1-0/+2
2021-06-25[X86] Add description of FXAM instructionSerge Pavlov1-1/+1
2021-06-15[X86] Schedule-model second (mask) output of GATHER instructionRoman Lebedev1-0/+4
2021-04-03[NFC][X86] Split VPMOV* AVX2 instructions into their own sched classRoman Lebedev1-0/+1
2020-06-13[X86] Add mayLoad flag to FARCALL*m/FARJMP memory instrutions. Add 'm' to the...Craig Topper1-2/+2
2020-05-19[X86] Split masked integer vector stores into vXi32/vXi64 variants (PR45975)....Andrea Di Biagio1-2/+4
2020-04-23[llvm] NFC: Fix trivial typo in rst and td filesKazuaki Ishizaki1-1/+1
2020-02-03[X86] Update the haswell and broadwell scheduler information for gather instr...Craig Topper1-47/+27
2020-01-17[X86] Split X87/SSE compare classes into WriteFCom + WriteFComXSimon Pilgrim1-0/+1
2019-09-02[X86][BtVer2] Fix latency and throughput of conditional SIMD store instructions.Andrea Di Biagio1-2/+6
2019-05-25[X86] Add zero idioms to the haswell, broadwell, and skylake schedule models....Craig Topper1-2/+85
2019-04-10[X86] Make _Int instructions the preferred instructon for the assembly parser...Craig Topper1-2/+2
2019-04-05[X86] Merge the different SETcc instructions for each condition code into sin...Craig Topper1-2/+26
2019-04-05[X86] Merge the different CMOV instructions for each condition code into sing...Craig Topper1-1/+26
2019-03-07[X86] Correct scheduler information for rotate by constant for Haswell, Broad...Craig Topper1-1/+9
2019-03-07[X86] Model ADC/SBB with immediate 0 more accurately in the Haswell scheduler...Craig Topper1-0/+30
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